Implement the following circuit:
module top_module (
input clk,
input in,
output out);
reg temp;
assign out = temp;
always@ (posedge clk) begin
temp <= in ^ out;
end
endmodule
Implement the following circuit:
module top_module (
input clk,
input in,
output out);
reg temp;
assign out = temp;
always@ (posedge clk) begin
temp <= in ^ out;
end
endmodule