TLV5620的FPGA控制器，产品拷机测试过

	`timescale 1ns / 1ps
	//**********************************************************
	//**********************************************************
	//(1)VO = (NUM/256)*REF*(1+RNG).
	//(2)data format : A1 A0 RNG D7 D6 D5 D4 D3 D2 D1 D0.
	//(3)With LOAD high, data is clocked into the DATA terminal 
	//on each falling edge of CLK.
	//(4)Once all data bits have been clocked in, LOAD is pulsed 
	//low to transfer the data from the serial-input register 
	//to the selected DAC.
	//**********************************************************
	//**********************************************************
	module DA4_TLV5620(
	input					CLK50M,
	input 				RST_N,
	//
	output 				DAC_CLK,
	output 				DAC_DATA,
	output 				DAC_LOAD_N,
	output 				DAC_LDAC_N,
	//
	input					DAC_VALID,
	input		[31 : 0]	PC_DATA_DAC, 
	output				DAC_DONE  
	);
	reg [5:0] div_cnt_50 = 6'b0;
	reg clk1m = 1'b0;
	reg dac_done_o = 1'b0;
	reg send_state = 1'b0;
	reg [5:0] send_cnt = 6'b0;
	reg [31:0] dac_data_reg = 32'b0;
	reg dac_load_n_o = 1'b1;
	reg dac_ldac_n_o = 1'b1;
	reg dac_clk_sel = 1'b0;
	reg dac_data_o = 1'b0;
	//**********************************************************
	//generate 1M clock
	//**********************************************************
	always @ (posedge CLK50M)
		begin
			if(~RST_N) div_cnt_50 <= 6'b0;
			else if(div_cnt_50 == 6'd49) div_cnt_50 <= 6'b0;
			else div_cnt_50 <= div_cnt_50 + 1;
		end
	//
	always @ (posedge CLK50M)
		begin
			if(~RST_N) clk1m <= 1'b0;
			else if(div_cnt_50 == 6'd24) clk1m <= ~clk1m;
			else if(div_cnt_50 == 6'd49) clk1m <= ~clk1m;
			else clk1m <= clk1m;
		end
	//**********************************************************
	//generate DAC_DONE
	//**********************************************************
	assign DAC_DONE = dac_done_o;
	always @ (posedge clk1m)
		begin
			if(~RST_N) dac_done_o <= 1'b0;
			else if(dac_done_o) dac_done_o <= 1'b0;
			else if(~send_state) 
				begin
					if(DAC_VALID) dac_done_o <= 1'b1;
					else dac_done_o <= 1'b0;
				end
			else dac_done_o <= 1'b0;
		end	
	//**********************************************************

    来自：https://bbs.21ic.com/icview-3012534-1-1.html