F28069M教程4-System Initialization

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原始教程入口： https://dev.ti.com/tirex/explore/node?node=AOpze8ebskysmgASY3VKSA__jEBbtmC__LATEST

本教程链接：
https://dev.ti.com/tirex/explore/content/c2000_academy_2.00.01.41_all/modules/Module_4_System_Initialization/module_4_system_initialization.html

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Overview

This module covers the operation of the OSC/PLL-based clock module and watchdog timer. Also, the general-purpose digital I/O, external interrupts, low power modes and the register protection will be covered.

Oscillator/PLL Clock Module

The device clock signals are derived from one of four clock sources:

Internal Oscillator 1 (INTOSC1)
Internal Oscillator 2 (INTOSC2)
External Oscillator (XTAL)
Auxiliary Clock Input (AUXCLKIN)

At power-up, the device is clocked from the on-chip 10 MHz oscillator INTOSC2. INTSOC2 is the primary internal clock source, and is the default system clock at reset. The device also includes a redundant on-chip 10 MHz oscillator INTOSC1. INTOSC1 is a backup clock source, which normally only clocks the watchdog timers and missing clock detection (MCD) circuit.

The device includes X1/X2 pins for supporting a quartz crystal or ceramic resonator. Alternatively, the clock output from an external oscillator may be fed to the device using the X1 pin or the AUXCLKIN input. For applicable devices, the AUXCLKIN input may be used as the bit clock source for the USB and CAN to meet the precise frequency requirements. Refer to the device-specific datasheet for the specific implementation.

The input clock can be multiplied using the on-chip phase locked loop (PLL) and divided down to produce the rated clock speed of the device or the desired clock frequency for a specific application. The PLL provides the capability to use the internal 10 MHz oscillator (or the external clock) and run the device at the rated clock frequency. If the input clock vanishes after the PLL is locked, the PLL will issue a limp mode clock of 1 to 4 MHz. Additionally, an internal device reset (or an interrupt) can be generated. The low speed peripheral clock prescaler is used to clock some of the communication peripherals.