Debugging issues on the AXI VDMA IP using XSDB Test the application

1. In SDK, build the application (select Project > Build All), program the FPGA (select Xilinx > Program FPGA) and launch the application (right click on the application > Run As > Launch on Hardware (System Debugger)).

You should not see any output on the monitor. If you check the LED DS19 on the ZC702 board, it should be off. This LED is monitoring the status of the video lock signal. As it is off, this means that we have an issue with the video pipe.

The AXI VDMA IP has a status register for both the write (S2MM) and the read (MM2S) interface which contains errors that the VDMA IP might face. We can start by reading the status register of the write interface at address 0x34 of the VDMA.

Debugging the write interface (S2MM)

To read this register we can use the XSCT console inside SDK.

1. Open the XSCT console by clicking Xilinx > XSCT console.

To read to a memory or a register using XSCT, we can use the command mrd. The address of the VDMA IP in this design is 0x43000000 (you can find this address in the system.hdf file under the hardware platform hw_0 in the Project Explorer). So in order to read the S2MM_VDMASR register, we need to read the address 0x43000034.

1. In the XSCT console, enter the following command:

mrd 0x43000034

We can see that the value read is 0x1D890.

 

Sometimes, errors can occur when starting the application. It is always a good idea to write 1’s in the status register, which will clear the register value, to make sure that the errors are still happening after startup.

1. Clear the S2MM status register and read its value back using the following commands:

mwr 0x43000034 0xFFFFFFFF
mrd 0x43000034

We can see that the value has changed slightly and is now 0x1D090. Looking at the register description in (PG020), we can analyze it as follows:

• Bit [0] value is 0: This means that the interface is running
• Bit [4] value is 1 (VDMAIntErr): This means that the VDMA IP is flagging errors.
• Bit [7] value is 1 (SOFEarlyErr): Start of Frame Early Error. This means that there is a mismatch between the VSIZE configuration and the number of lines in the incoming stream.
• Bit [15] value is 1 (EOLLateErr): End of Line Late Error. This indicates that there is a mismatch between the HSIZE configuration and the number of pixels per line in the incoming stream.

I recommend you to first try to debug the issues here without reading the part below which gives the solution.

We will start by looking at the SOFEarlyErr error. We can check the code to try to find the root cause of this error.

In vdma_app_zc702.c, on line 43, we can see that the TPG is configured to output a frame with 600 lines.

Note: if you want to display the line numbers in SDK, just right-click on the left side of the text editor window and click Show line number.

XV_tpg_Set_height(&tpg_inst, 600);

 However, on line 70, we can see that the VSIZE is set to 800.

1. You can fix the issue with the following code:

/*Set S2MM_VSIZE (A0h) to the number of lines per frame.*/
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA0, 600);

Now we can check the EOLLateErr by looking at the code.

We can see that on line 44, the TPG is configured to output a frame with 800 pixels per lines:

XV_tpg_Set _width(&tpg_inst, 800);

On line 68, we can see that HSIZE is also set to 800:

/*Set S2MM_HSIZE (A4h)*/
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, 800);

This is a common error. HISZE describes the horizontal size not in number of pixels per line, but in number of bytes.

In the Vivado design (refer to the previous video series), the AXI4-Stream interface inputted to the AXI VDMA is 16-bit (or 2 bytes) width, and we are sending only 1 pixel per clock cycle. This means that we have to multiply the line size by 2 to configure the HSIZE.

1. You can fix the issue with the following code:

/*Set S2MM_HSIZE (A4h)*/
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, 800*2);

1. Re-build the application (Select Project > Build All), re-program the FPGA (Select Xilinx > Program FPGA) and re-launch the application (Right click on the application > Run As > Launch on Hardware (System Debugger)).
    
2. Clear the S2MM status register and read its value back using the following commands:

mwr 0x43000034 0xFFFFFFFF
mrd 0x43000034

The value we read now is 0x10000 which means that we do not have any errors on the S2MM interface.

However, we still cannot see any output on the monitor.

We can now look at the status register of the read interface (MM2S) at address 0x04.

Debugging the read interface (MM2S)

 

1. Clear the MM2S status register and read its value back using the following commands:

mwr 0x43000004 0xFFFFFFFF
mrd 0x43000004

You should read the value 0x10041. Looking at the register description in (PG020), we can analyze it as follows:

• Bit [0] value is 1: Which means that the channel is halted
• Bit [6] value is 1 (VDMADecErr): VDMA Decode Error. This means that we are reading at an invalid address.

This is the code configuring the frame buffers for the read interface (from line 76):

/*Set MM2S_Start_Address1 (5Ch) through MM2S_Start_Address 3 (64h) to their  required locations.*/
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C, 0x40000000);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x60, 0x100F0000);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x64, 0x101E0000);

We can see that the first frame buffer is set at address 0x40000000.

This is incorrect as this is over the address range of the DDR (and there is no memory mapped interface at this address)

1. You can fix the issue with the following code:

/*Set MM2S_Start_Address1 (5Ch) through MM2S_Start_Address 3 (64h) to their  required locations.*/
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C, 0x10000000);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x60, 0x100F0000);
Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x64, 0x101E0000);

1. Re-build the application (Select Project > Build All), re-program the FPGA (Select Xilinx > Program FPGA) and re-launch the application (Right click on the application > Run As > Launch on Hardware (System Debugger)).

You should now see a color bar pattern displayed on the monitor.

You can also cross check with the MM2S status register value to confirm that we do not have any errors remaining in the VDMA.