OK6410 UBOOT移植（2）

OK6410 UBOOT移植（2） 

 

2012-05-30 20:14:31|  分类： linux |字号 订阅

修改启动代码：

 

修改cpu/arm1176/start.s,

 

修改的第一处是

#ifndef CONFIG_NAND_SPL

/*

 *flush v4 I/D caches

 */

mov r0, #0

mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4cache */

mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB*/

/*

 *disable MMU stuff andcaches//

 */

mrc p15, 0, r0, c1, c0, 0

bic r0, r0, #0x00002300 @ clear bits 13,9:8 (--V- --RS)

bic r0, r0, #0x00000087 @ clear bits 7, 2:0(B--- -CAM)

orr r0, r0, #0x00000002 @ set bit 2 (A)Align

orr r0, r0, #0x00001000 @ set bit 12 (I)I-Cache

mcr p15, 0, r0, c1, c0, 0//从后面拷贝过来的

///以下的注释掉

 

/* Prepare to disable the MMU */

//adr r1, mmu_disable_phys

/* We presume we're within the first 1024bytes */

//and r1, r1, #0x3fc

//ldr r2, _TEXT_PHY_BASE

//ldr r3, =0xfff00000

//and r2, r2, r3

//orr r2, r2, r1

//b mmu_disable

//.align 5

/* Run in a single cache-line */

//mmu_disable:

// mcr p15, 0, r0, c1, c0, 0

// nop

// nop

// mov pc, r2

/ 

#endif

 

修改的第二处在

bl lowlevel_init /* go setup pll,mux,memory*/  之后

 

 

/* when we already run in ram, we don'tneed to relocateU-Boot.

* and actually, memory controller must beconfigured before U-Boot

* is running in ram.

*/

 ldrr0, =0xff000fff

 bicr1, pc, r0  /* r0 <- current base addrof code */

 ldrr2, _TEXT_BASE  /* r1 <- original baseaddr in ram */

 bicr2, r2, r0  /* r0 <- current base addrof code */

 cmp    r1, r2                  /* comparer0, r1                  */

 beq     after_copy  /* r0 == r1 then skipflash copy   */

#ifdef CONFIG_BOOT_NAND

  movr0, #0x1000

 blcopy_from_nand

#endif

after_copy:/

#ifdef CONFIG_ENABLE_MMU  

 

第三处在

 

#ifndef CONFIG_NAND_SPL

/*

 * weassume that cache operation is done before. (eg. cleanup_before_linux())

 *actually, we don't need to do anything about cache if not use d-cache in

 *U-Boot. So, in this function we clean only MMU. by scsuh

 *

 *void theLastJump(void *kernel, int arch_num, uint boot_params);

 */

#ifdef CONFIG_ENABLE_MMU

 .globl theLastJump

theLastJump: 

之前加上以下语句

 

/*

 *copy U-Boot to SDRAM and jump to ram (from NAND or OneNAND)

 *r0: size to be compared

 *Load 1'st 2blocks to RAM because U-boot's size is larger than 1block(128k) size

 *///

.globl copy_from_nand

 

copy_from_nand:

  movr10, lr  /* save return address */

 

  movr9, r0

 /*get ready to call C functions */

 

 

ldr sp, _TEXT_PHY_BASE /* setup temp stackpointer */

 subsp, sp, #12

 movfp, #0   /* no previous frame, so fp=0 */

 movr9, #0x1000

 blcopy_uboot_to_ram           //此函数需要添加，稍后说明。

3: tst r0, #0x0

  bnecopy_failed

  ldrr0, =0x0c000000

  ldrr1, _TEXT_PHY_BASE

1: ldr r3, [r0], #4

  ldrr4, [r1], #4

 teqr3, r4

 bnecompare_failed /* not matched */

 subsr9, r9, #4

 bne1b

4: mov lr, r10  /* all is OK */

  movpc, lr

copy_failed:

 nop   /* copy from nand failed */

  

b copy_failed

compare_failed:

 nop   /*compare failed */

 bcompare_failed  

 

 

 

 

 

 

我的代码start.s

/*

 * armboot - Startup Code for S3C6400/ARM1176 CPU-core

 *

 *Copyright (c) 2007 Samsung Electronics

 *

 *Copyright (C) 2008

 *Guennadi Liakhovetki, DENX Software Engineering, <lg@denx.de>

 *

 *See file CREDITS for list of people who contributed to this

 *project.

 *

 *This program is free software; you can redistribute it and/or

 *modify it under the terms of the GNU General Public License as

 *published by the Free Software Foundation; either version 2 of

 *the License, or (at your option) any later version.

 *

 *This program is distributed in the hope that it will be useful,

 *but WITHOUT ANY WARRANTY; without even the implied warranty of

 *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the

 *GNU General Public License for more details.

 *

 *You should have received a copy of the GNU General Public License

 *along with this program; if not, write to the Free Software

 *Foundation, Inc., 59 Temple Place, Suite 330, Boston,

 * MA02111-1307 USA

 *

 *2007-09-21 - Restructured codes by jsgood (jsgood.yang@samsung.com)

 *2007-09-21 - Added MoviNAND and OneNAND boot codes by

 *jsgood (jsgood.yang@samsung.com)

 *Base codes by scsuh (sc.suh)

 */

 

#include <config.h>

#include <version.h>

#ifdef CONFIG_ENABLE_MMU

#include <asm/proc/domain.h>

#endif

#include <asm/arch/s3c6400.h>

 

#if !defined(CONFIG_ENABLE_MMU) &&!defined(CONFIG_SYS_PHY_UBOOT_BASE)

#define CONFIG_SYS_PHY_UBOOT_BASECONFIG_SYS_UBOOT_BASE

#endif

 

/*

 *************************************************************************

 *

 *Jump vector table as in table 3.1 in [1]

 *

 *************************************************************************

 */

 

.globl _start

_start: b reset

#ifndef CONFIG_NAND_SPL

ldr pc, _undefined_instruction

ldr pc, _software_interrupt

ldr pc, _prefetch_abort

ldr pc, _data_abort

ldr pc, _not_used

ldr pc, _irq

ldr pc, _fiq

 

_undefined_instruction:

.word undefined_instruction

_software_interrupt:

.word software_interrupt

_prefetch_abort:

.word prefetch_abort

_data_abort:

.word data_abort

_not_used:

.word not_used

_irq:

.word irq

_fiq:

.word fiq

_pad:

.word 0x12345678 /* now 16*4=64 */

#else

. = _start + 64

#endif

 

.global _end_vect

_end_vect:

.balignl 16,0xdeadbeef

/*

 *************************************************************************

 *

 *Startup Code (reset vector)

 *

 * doimportant init only if we don't start from memory!

 *setup Memory and board specific bits prior to relocation.

 *relocate armboot to ram

 *setup stack

 *

 *************************************************************************

 */

 

_TEXT_BASE:

.word TEXT_BASE

 

/*

 *Below variable is very important because we use MMU in U-Boot.

 *Without it, we cannot run code correctly before MMU is ON.

 * byscsuh.

 */

_TEXT_PHY_BASE:

.word CONFIG_SYS_PHY_UBOOT_BASE

 

.globl _armboot_start

_armboot_start:

.word _start

 

/*

 *These are defined in the board-specific linker script.

 */

.globl _bss_start

_bss_start:

.word __bss_start

 

.globl _bss_end

_bss_end:

.word _end

 

/*

 *the actual reset code

 */

 

reset:

/*

* set the cpu to SVC32 mode

*/

mrs r0, cpsr

//bic r0, r0, #0x3f

bic r0, r0, #0x3f

orr r0, r0, #0xd3

msr cpsr, r0

 

/*

 *************************************************************************

 *

 *CPU_init_critical registers

 *

 *setup important registers

 *setup memory timing

 *

 *************************************************************************

 */

/*

* we do sys-critical inits only at reboot,

* not when booting from ram!

*/

cpu_init_crit:

/*

* When booting from NAND - it hasdefinitely been a reset, so, no need

* to flush caches and disable the MMU

*/

#ifndef CONFIG_NAND_SPL

/*

* flush v4 I/D caches

*/

mov r0, #0

mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4cache */

mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB*/

 

/*

* disable MMU stuff andcaches//

*/

mrc p15, 0, r0, c1, c0, 0

bic r0, r0, #0x00002300 @ clear bits 13,9:8 (--V- --RS)

bic r0, r0, #0x00000087 @ clear bits 7, 2:0(B--- -CAM)

orr r0, r0, #0x00000002 @ set bit 2 (A)Align

orr r0, r0, #0x00001000 @ set bit 12 (I)I-Cache

mcr p15, 0, r0, c1, c0, 0

/* Prepare to disable the MMU */

//adr r1, mmu_disable_phys

/* We presume we're within the first 1024bytes */

//and r1, r1, #0x3fc

//ldr r2, _TEXT_PHY_BASE

//ldr r3, =0xfff00000

//and r2, r2, r3

//orr r2, r2, r1

//b mmu_disable

 

//.align 5

/* Run in a single cache-line */

//mmu_disable:

// mcr p15, 0, r0, c1, c0, 0

// nop

// nop

// mov pc, r2

//

#endif

 

mmu_disable_phys:

/* Peri port setup */

ldr r0, =0x70000000

orr r0, r0, #0x13

mcr p15,0,r0,c15,c2,4       @ 256M (0x70000000 - 0x7fffffff)

 

/*

* Go setup Memory and board specific bitsprior to relocation.

*/

bl lowlevel_init /* go setup pll,mux,memory*/

/* when we already run in ram, we don'tneed to relocateU-Boot.

* and actually, memory controller must beconfigured before U-Boot

* is running in ram.

*/

ldr r0, =0xff000fff

bic r1, pc, r0  /* r0 <- current base addr of code */

ldr r2, _TEXT_BASE  /* r1 <- original base addr in ram */

bic r2, r2, r0  /* r0 <- current base addr of code */

cmp    r1, r2                  /* comparer0, r1                  */

beq    after_copy  /* r0 == r1 then skipflash copy   */

 

#ifdef CONFIG_BOOT_NAND

  movr0, #0x1000

bl copy_from_nand

#endif

after_copy:/

#ifdef CONFIG_ENABLE_MMU

enable_mmu:

/* enable domain access */

ldr r5, =0x0000ffff

mcr p15, 0, r5, c3, c0, 0 /* load domainaccess register */

 

/* Set the TTB register */

ldr r0, _mmu_table_base

ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE

ldr r2, =0xfff00000

bic r0, r0, r2

orr r1, r0, r1

mcr p15, 0, r1, c2, c0, 0

 

/* Enable the MMU */

mrc p15, 0, r0, c1, c0, 0

orr r0, r0, #1 /* Set CR_M to enable MMU */

 

/* Prepare to enable the MMU */

adr r1, skip_hw_init

and r1, r1, #0x3fc

ldr r2, _TEXT_BASE

ldr r3, =0xfff00000

and r2, r2, r3

orr r2, r2, r1

b mmu_enable

 

.align 5

/* Run in a single cache-line */

mmu_enable:

 

mcr p15, 0, r0, c1, c0, 0

nop

nop

mov pc, r2

#endif

 

skip_hw_init:

/* Set up the stack    */

stack_setup:

ldr r0, =CONFIG_SYS_UBOOT_BASE /* base ofcopy in DRAM    */

sub r0, r0, #CONFIG_SYS_MALLOC_LEN /*malloc area                      */

sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /*bdinfo                        */

sub sp, r0, #12 /* leave 3 words forabort-stack    */

 

clear_bss:

ldr r0, _bss_start /* find start of bsssegment        */

ldr r1, _bss_end /* stop here                        */

mov r2, #0 /* clear                            */

 

clbss_l:

str r2, [r0] /* clear loop...                    */

add r0, r0, #4

cmp r0, r1

ble clbss_l

 

#ifndef CONFIG_NAND_SPL

ldr pc, _start_armboot

 

_start_armboot:

.word start_armboot

#else

b nand_boot

/* .word nand_boot*/

#endif

 

#ifdef CONFIG_ENABLE_MMU

_mmu_table_base:

.word mmu_table

#endif

/*

 *copy U-Boot to SDRAM and jump to ram (from NAND or OneNAND)

 *r0: size to be compared

 *Load 1'st 2blocks to RAM because U-boot's size is larger than 1block(128k) size

 *///

.globl copy_from_nand

 

copy_from_nand:

mov r10, lr /* save return address */

 

  movr9, r0

 /*get ready to call C functions */

  ldrsp, _TEXT_PHY_BASE /* setup temp stack pointer */

sub sp, sp, #12

mov fp, #0  /* no previous frame, so fp=0 */

mov r9, #0x1000

bl copy_uboot_to_ram           //此函数需要添加，稍后说明。

 

3: tst r0, #0x0

  bnecopy_failed

 

  ldrr0, =0x0c000000

  ldrr1, _TEXT_PHY_BASE

1: ldr r3, [r0], #4

  ldrr4, [r1], #4

teq r3, r4

bne compare_failed /* not matched */

subs r9, r9, #4

bne 1b

 

4: mov lr, r10  /* all is OK */

  movpc, lr

 

copy_failed:

 nop   /* copy from nand failed */

  bcopy_failed

 

compare_failed:

nop  /* compare failed */

b compare_failed

#ifndef CONFIG_NAND_SPL

/*

 * weassume that cache operation is done before. (eg. cleanup_before_linux())

 *actually, we don't need to do anything about cache if not use d-cache in

 *U-Boot. So, in this function we clean only MMU. by scsuh

 *

 *void theLastJump(void *kernel, int arch_num, uint boot_params);

 */

 

 

 

 

#ifdef CONFIG_ENABLE_MMU

.globl theLastJump

theLastJump:

mov r9, r0

ldr r3, =0xfff00000

ldr r4, _TEXT_PHY_BASE

adr r5, phy_last_jump

bic r5, r5, r3

orr r5, r5, r4

mov pc, r5

phy_last_jump:

/*

* disable MMU stuff

*/

mrc p15, 0, r0, c1, c0, 0

bic r0, r0, #0x00002300 /* clear bits 13,9:8 (--V- --RS) */

bic r0, r0, #0x00000087 /* clear bits 7,2:0 (B--- -CAM) */

orr r0, r0, #0x00000002 /* set bit 2 (A)Align */

orr r0, r0, #0x00001000 /* set bit 12 (I)I-Cache */

mcr p15, 0, r0, c1, c0, 0

 

mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB*/

 

mov r0, #0

mov pc, r9

#endif

/*

 *************************************************************************

 *

 *Interrupt handling

 *

 *************************************************************************

 */

@

@ IRQ stack frame.

@

#define S_FRAME_SIZE 72

 

#define S_OLD_R0 68

#define S_PSR 64

#define S_PC 60

#define S_LR 56

#define S_SP 52

 

#define S_IP 48

#define S_FP 44

#define S_R10 40

#define S_R9 36

#define S_R8 32

#define S_R7 28

#define S_R6 24

#define S_R5 20

#define S_R4 16

#define S_R3 12

#define S_R2 8

#define S_R1 4

#define S_R0 0

 

#define MODE_SVC 0x13

#define I_BIT 0x80

 

/*

 *use bad_save_user_regs for abort/prefetch/undef/swi ...

 */

 

.macro bad_save_user_regs

/* carve out a frame on current user stack*/

sub sp, sp, #S_FRAME_SIZE

/* Save user registers (now in svc mode)r0-r12 */

stmia sp, {r0 - r12}

 

ldr r2, _armboot_start

sub r2, r2, #(CONFIG_SYS_MALLOC_LEN)

/* set base 2 words into abort stack */

sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)

/* get values for "aborted" pcand cpsr (into parm regs) */

ldmia r2, {r2 - r3}

/* grab pointer to old stack */

add r0, sp, #S_FRAME_SIZE

 

add r5, sp, #S_SP

mov r1, lr

/* save sp_SVC, lr_SVC, pc, cpsr */

stmia r5, {r0 - r3}

/* save current stack into r0 (paramregister) */

mov r0, sp

.endm

 

.macro get_bad_stack

/* setup our mode stack (enter in bankedmode) */

ldr r13, _armboot_start

/* move past malloc pool */

sub r13, r13, #(CONFIG_SYS_MALLOC_LEN)

/* move to reserved a couple spots forabort stack */

sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE +8)

 

/* save caller lr in position 0 of savedstack */

str lr, [r13]

/* get the spsr */

mrs lr, spsr

/* save spsr in position 1 of saved stack*/

str lr, [r13, #4]

 

/* prepare SVC-Mode */

mov r13, #MODE_SVC

@ msr spsr_c, r13

/* switch modes, make sure moves willexecute */

msr spsr, r13

/* capture return pc */

mov lr, pc

/* jump to next instruction & switchmodes. */

movs pc, lr

.endm

 

.macro get_bad_stack_swi

/* space on current stack for scratch reg.*/

sub r13, r13, #4

/* save R0's value. */

str r0, [r13]

/* get data regions start */

ldr r0, _armboot_start

/* move past malloc pool */

sub r0, r0, #(CONFIG_SYS_MALLOC_LEN)

/* move past gbl and a couple spots forabort stack */

sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8)

/* save caller lr in position 0 of savedstack */

str lr, [r0]

/* get the spsr */

mrs r0, spsr

/* save spsr in position 1 of saved stack*/

str lr, [r0, #4]

/* restore r0 */

ldr r0, [r13]

/* pop stack entry */

add r13, r13, #4

.endm

 

/*

 *exception handlers

 */

.align 5

undefined_instruction:

get_bad_stack

bad_save_user_regs

bl do_undefined_instruction

 

.align 5

software_interrupt:

get_bad_stack_swi

bad_save_user_regs

bl do_software_interrupt

 

.align 5

prefetch_abort:

get_bad_stack

bad_save_user_regs

bl do_prefetch_abort

 

.align 5

data_abort:

get_bad_stack

bad_save_user_regs

bl do_data_abort

 

.align 5

not_used:

get_bad_stack

bad_save_user_regs

bl do_not_used

 

.align 5

irq:

get_bad_stack

bad_save_user_regs

bl do_irq

 

.align 5

fiq:

get_bad_stack

bad_save_user_regs

bl do_fiq

#endif /* CONFIG_NAND_SPL */