ADC 检测 SONIX 中断方式

chip	sn8p2711A

.data
			adc_buf	 		ds		1
			acc_buf			ds		1
			pflag_buf		ds		1
				
.code

			org	00h
			jmp	main
			org	08h
			jmp	isr

			org	10h
main:
			b0bset	fadenb				// Enable ADC circuit 
			call	delay100us			// Delay 100us
			mov	a,#0feh
			b0mov	p4ur,a				// Disable P4.0 pull-up resistor
			b0bclr	fp40m				// Set P40 as input pin
			mov	a,#01h
			b0mov	p4con,a				// Set P40 as pure analog input
			mov	a,#40h			// To set 8-bit and  Fcpu/1.
			b0mov	adr,a		
			mov	a,#90h			// Enable ADC and set AIN0 input
			b0mov	adm,a
			b0bset	fadcien				// Enable ADC interrupt service
			b0bclr	fadcirq				// Clear ADC interrupt request flag
			b0bset	fgie				// Enable GIE		
			b0bset	fads				// To start conversion
//===============================================================
//										
//			User	 code
//						
//===============================================================

			jmp	main
	



//======================================================
//        interrupt code 
//======================================================
isr:
			mov	acc_buf,a				// Push ACC to buffer
			mov	a,pflag
			b0mov	pflag_buf,a				// Push PFLAG to buffer
isr_adc:
			b0bts1	fadcien					// Check adcien
			jmp	isr90					
			b0bts1	fadcirq					// Check adcirp
			jmp	isr90					
			b0bclr	fadcirq
			b0mov	a,adb					// To get AIN0 input data 
			b0mov	adc_buf,a 
isr90:
			mov	a,pflag_buf
			b0mov	pflag,a					// Pop pflag_buf to pflag
			mov	a,acc_buf				// Pop acc_buf to acc
			reti



1 1 1 PRODUCT OVERVIEW 1.1 FEATURES  Features Selection Table CHIP ROM RAM Stack Timer I/O ADC ADC Int. Ref. Green Mode PWM Wake-up Pin No. Package TC0 TC1 Buzzer SN8P2711A 1K 64 4 V V 12 5+1 V V 2 5 DIP14/SOP14/ SSOP16  Memory configuration  Two 8-bit Timer/Counter ROM size: 1K * 16 bits. One 8-bit timer with external event counter, RAM size: 64 * 8 bits. Buzzer0 and PWM0. (TC0). One 8-bit timer with external event counter,  4 levels stack buffer. Buzzer1 and PWM1. (TC1).  5 interrupt sources  5+1 channel 12-bit SAR ADC. 3 internal interrupts: TC0, TC1, ADC Five external ADC input 2 external interrupt: INT0, INT1 One internal battery measurement Internal AD reference voltage (VDD, 4V, 3V, 2V).  I/O pin configuration Bi-directional: P0, P4, P5.  On chip watchdog timer and clock source is Input only: P0.4. Internal low clock RC type (16KHz(3V), 32KHz(5V)) Pull-up resisters: P0, P4, P5. Wakeup: P0 level change.  4 system clocks ADC input pin: P4.0~P4.4. External high clock: RC type up to 10 MHz External Interrupt trigger edge: External high clock: Crystal type up to 16 MHz P0.0 controlled by PEDGE register. Internal high clock: 16MHz RC type P0.1 is falling edge trigger only. Internal low clock: RC type 16KHz(3V), 32KHz(5V)  3-Level LVD  4 operating modes Reset system and power monitor. Normal mode: Both high and low clock active Slow mode: Low clock only.  Powerful instructions Sleep mode: Both high and low clock stop Instruction‟s length is one word. Green mode: Periodical wakeup by TC0 timer Most of instructions are one cycle only. All ROM area JMP/CALL instruction.  Package (Chip form support) All ROM area lookup table function (MOVC). DIP 14 pin SOP 14 pin  Fcpu (Instruction cycle) SSOP 16 pin Fcpu = Fosc/1, Fosc/2, Fosc/4, Fosc/8, Fosc/16,
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