mini6410移植全攻略（4）--uboot移植之支持nand flansh启动(中)

四、修改有关的信息：

本文章由muge0913编写，仅供技术交流转载请注明出处：

http://blog.csdn.net/muge0913/article/details/7168325

1、

串口中打印出来的信息大多数来自board.c文件

print_cpuinfo函数在/*arch/arm/cpu/arm1176/s3c64xx/speed.c*/实现

更改相应的信息即可。

2、checkboard函数在/*board/samsung/th6410/th6410.c*/实现，更改相应的信息即可。

3、同时屏蔽

env_init, /* initialize environment */ init_baudrate, /* initialze baudrate settings */ // serial_init, /* serial communications setup */ console_init_f, /* stage 1 init of console */ display_banner, /* say that we are here */
串口初始化在lowlevel_init.S中实现，其代码如下，这是经过修改后的代码，因为工作量问题我们不再具体讲述。

五、lovlevel_init.S代码分析：

#include <config.h> #include <version.h> #include <asm/arch/s3c6400.h> #ifdef CONFIG_SERIAL1 #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART0_OFFSET) #elif defined(CONFIG_SERIAL2) #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART1_OFFSET) #else #define ELFIN_UART_CONSOLE_BASE (ELFIN_UART_BASE + ELFIN_UART2_OFFSET) #endif _TEXT_BASE: .word TEXT_BASE .globl lowlevel_init lowlevel_init: mov r12, lr /* LED on only #8 在这里我们不做处理*/ /* 禁止看门狗*/ ldr r0, =0x7e000000 @0x7e004000 orr r0, r0, #0x4000 mov r1, #0 str r1, [r0] /*禁止外部中断*/ ldr r0, =(ELFIN_GPIO_BASE+EINTPEND_OFFSET) /*EINTPEND*/ ldr r1, [r0] str r1, [r0] ldr r0, =ELFIN_VIC0_BASE_ADDR @0x71200000 ldr r1, =ELFIN_VIC1_BASE_ADDR @0x71300000 mvn r3, #0x0 str r3, [r0, #oINTMSK] str r3, [r1, #oINTMSK] @ 设置IRQ mov r3, #0x0 str r3, [r0, #oINTMOD] str r3, [r1, #oINTMOD] mov r3, #0x0 str r3, [r0, #oVECTADDR] str r3, [r1, #oVECTADDR] /* 初始化系统时钟 */ bl system_clock_init /* 初始化串口 */ bl uart_asm_init #if defined(CONFIG_NAND) /* simple init for NAND */ bl nand_asm_init #endif /*初始化存储控制*/ bl mem_ctrl_asm_init #if 1 ldr r0, =(ELFIN_CLOCK_POWER_BASE+RST_STAT_OFFSET) ldr r1, [r0] bic r1, r1, #0xfffffff7 cmp r1, #0x8 beq wakeup_reset #endif 1: ldr r0, =ELFIN_UART_BASE ldr r1, =0x4b4b4b4b str r1, [r0, #UTXH_OFFSET] mov lr, r12 mov pc, lr #if 1 wakeup_reset: /*Clear wakeup status register*/ ldr r0, =(ELFIN_CLOCK_POWER_BASE+WAKEUP_STAT_OFFSET) ldr r1, [r0] str r1, [r0] /*LED test*/ ldr r0, =ELFIN_GPIO_BASE ldr r1, =0x3000 str r1, [r0, #GPNDAT_OFFSET] /*Load return address and jump to kernel*/ ldr r0, =(ELFIN_CLOCK_POWER_BASE+INF_REG0_OFFSET) ldr r1, [r0] /* r1 = physical address of s3c6400_cpu_resume function*/ mov pc, r1 /*Jump to kernel (sleep-s3c6400.S)*/ nop nop #endif /* * system_clock_init: Initialize core clock and bus clock. * void system_clock_init(void) */ system_clock_init: ldr r0, =ELFIN_CLOCK_POWER_BASE @0x7e00f000 #ifdef CONFIG_SYNC_MODE ldr r1, [r0, #OTHERS_OFFSET] mov r2, #0x40 orr r1, r1, r2 str r1, [r0, #OTHERS_OFFSET] nop nop nop nop nop ldr r2, =0x80 orr r1, r1, r2 str r1, [r0, #OTHERS_OFFSET] check_syncack: ldr r1, [r0, #OTHERS_OFFSET] ldr r2, =0xf00 and r1, r1, r2 cmp r1, #0xf00 bne check_syncack #else /* ASYNC Mode */ nop nop nop nop nop ldr r1, [r0, #OTHERS_OFFSET] bic r1, r1, #0xC0 orr r1, r1, #0x40 str r1, [r0, #OTHERS_OFFSET] wait_for_async: ldr r1, [r0, #OTHERS_OFFSET] and r1, r1, #0xf00 cmp r1, #0x0 bne wait_for_async ldr r1, [r0, #OTHERS_OFFSET] bic r1, r1, #0x40 str r1, [r0, #OTHERS_OFFSET] #endif mov r1, #0xff00 orr r1, r1, #0xff str r1, [r0, #APLL_LOCK_OFFSET] str r1, [r0, #MPLL_LOCK_OFFSET] str r1, [r0, #EPLL_LOCK_OFFSET] /* CLKUART(=66.5Mhz) = CLKUART_input(532/2=266Mhz) / (UART_RATIO(3)+1) */ /* CLKUART(=50Mhz) = CLKUART_input(400/2=200Mhz) / (UART_RATIO(3)+1) */ /* Now, When you use UART CLK SRC by EXT_UCLK1, We support 532MHz & 400MHz value */ #if defined(CONFIG_CLKSRC_CLKUART) ldr r1, [r0, #CLK_DIV2_OFFSET] bic r1, r1, #0x70000 orr r1, r1, #0x30000 str r1, [r0, #CLK_DIV2_OFFSET] #endif ldr r1, [r0, #CLK_DIV0_OFFSET] /*Set Clock Divider*/ bic r1, r1, #0x30000 bic r1, r1, #0xff00 bic r1, r1, #0xff ldr r2, =CLK_DIV_VAL orr r1, r1, r2 str r1, [r0, #CLK_DIV0_OFFSET] ldr r1, =APLL_VAL str r1, [r0, #APLL_CON_OFFSET] ldr r1, =MPLL_VAL str r1, [r0, #MPLL_CON_OFFSET] ldr r1, =0x80200203 /* FOUT of EPLL is 96MHz */ str r1, [r0, #EPLL_CON0_OFFSET] ldr r1, =0x0 str r1, [r0, #EPLL_CON1_OFFSET] ldr r1, [r0, #CLK_SRC_OFFSET] /* APLL, MPLL, EPLL select to Fout */ #if defined(CONFIG_CLKSRC_CLKUART) ldr r2, =0x2007 #else ldr r2, =0x7 #endif orr r1, r1, r2 str r1, [r0, #CLK_SRC_OFFSET] /* wait at least 200us to stablize all clock */ mov r1, #0x10000 1: subs r1, r1, #1 bne 1b #if 0 mrc p15, 0, r0, c1, c0, 0 orr r0, r0, #0xc0000000 /* clock setting in MMU */ mcr p15, 0, r0, c1, c0, 0 #endif #ifdef CONFIG_SYNC_MODE /* Synchronization for VIC port */ ldr r1, [r0, #OTHERS_OFFSET] orr r1, r1, #0x20 str r1, [r0, #OTHERS_OFFSET] #else ldr r1, [r0, #OTHERS_OFFSET] bic r1, r1, #0x20 str r1, [r0, #OTHERS_OFFSET] #endif mov pc, lr /* * uart_asm_init: Initialize UART in asm mode, 115200bps fixed. * void uart_asm_init(void) */ uart_asm_init: /* set GPIO to enable UART */ @ GPIO setting for UART ldr r0, =ELFIN_GPIO_BASE ldr r1, =0x22222222 str r1, [r0, #GPACON_OFFSET] ldr r1, =0x2222 str r1, [r0, #GPBCON_OFFSET] ldr r0, =ELFIN_UART_CONSOLE_BASE @0x7F005000 mov r1, #0x0 str r1, [r0, #UFCON_OFFSET] str r1, [r0, #UMCON_OFFSET] mov r1, #0x3 @was 0. str r1, [r0, #ULCON_OFFSET] #if defined(CONFIG_CLKSRC_CLKUART) ldr r1, =0xe45 /* UARTCLK SRC = 11 => EXT_UCLK1*/ #else ldr r1, =0x245 /* UARTCLK SRC = x0 => PCLK */ #endif str r1, [r0, #UCON_OFFSET] #if defined(CONFIG_UART_50) ldr r1, =0x1A #elif defined(CONFIG_UART_66) ldr r1, =0x22 #else ldr r1, =0x1A #endif str r1, [r0, #UBRDIV_OFFSET] #if defined(CONFIG_UART_50) ldr r1, =0x3 #elif defined(CONFIG_UART_66) ldr r1, =0x1FFF #else ldr r1, =0x3 #endif str r1, [r0, #UDIVSLOT_OFFSET] ldr r1, =0x4f4f4f4f str r1, [r0, #UTXH_OFFSET] @'O' mov pc, lr /* * Nand Interface Init for SMDK6400 */ nand_asm_init: ldr r0, =ELFIN_NAND_BASE ldr r1, [r0, #NFCONF_OFFSET] orr r1, r1, #0x70 orr r1, r1, #0x7700 str r1, [r0, #NFCONF_OFFSET] ldr r1, [r0, #NFCONT_OFFSET] orr r1, r1, #0x03 str r1, [r0, #NFCONT_OFFSET] mov pc, lr #ifdef CONFIG_ENABLE_MMU /* * MMU Table for SMDK6400 */ /* form a first-level section entry */ .macro FL_SECTION_ENTRY base,ap,d,c,b .word (\base << 20) | (\ap << 10) | \ (\d << 5) | (1<<4) | (\c << 3) | (\b << 2) | (1<<1) .endm .section .mmudata, "a" .align 14 // the following alignment creates the mmu table at address 0x4000. .globl mmu_table mmu_table: .set __base,0 // 1:1 mapping for debugging .rept 0xA00 FL_SECTION_ENTRY __base,3,0,0,0 .set __base,__base+1 .endr // access is not allowed. .rept 0xC00 - 0xA00 .word 0x00000000 .endr // 128MB for SDRAM 0xC0000000 -> 0x50000000 .set __base, 0x500 .rept 0xC80 - 0xC00 FL_SECTION_ENTRY __base,3,0,1,1 .set __base,__base+1 .endr // access is not allowed. .rept 0x1000 - 0xc80 .word 0x00000000 .endr #endif

本文章由muge0913编写，仅供技术交流转载请注明出处

http://blog.csdn.net/muge0913/article/details/7168325