一、Debug LOG串口更改
orangepi 4G iot的默认的log调试串口是在板子后面的，使用起来不方便，之前UART0焊接不好导致焊盘弄坏了，没办法，准备修改成插针的40pin引脚的的UART1 （即使UTXD1和URXD1）
本文就是将板子默认debug串口从UART0改成了UART1
40 pin串口UART1：
二：UART相关代码以及设置修改
修改PIN脚的工具
修改的地方可以参考以下代码
1: /home/ubuntu/Mediatek/code/vendor/mediatek/proprietary/bootable/bootloader/preloader/custom/bd6737m_35g_b_m0/cust_bldr.mak
###################################################################
# Include Project Feautre (cust_bldr.h)
###################################################################
#ifeq ("$(MTK_EMMC_SUPPORT)","yes")
ifdef MTK_EMMC_SUPPORT
CFG_BOOT_DEV :=BOOTDEV_SDMMC
else
CFG_BOOT_DEV :=BOOTDEV_NAND
endif
CFG_UART_LOG :=UART2
CFG_UART_META :=UART2
#CFG_UART_LOG :=UART1 -> 20220515
#CFG_UART_META :=UART1
CFG_USB_UART_SWITCH := 02：/home/ubuntu/Mediatek/code/vendor/mediatek/proprietary/bootable/bootloader/preloader/platform/mt6735/default.mak
###################################################################
# Default Internal Feautre
###################################################################
HW_INIT_ONLY :=
###################################################################
# Default Project Feautre (cust_bldr.h)
###################################################################
CFG_BOOT_DEV :=BOOTDEV_SDMMC
CFG_FPGA_PLATFORM :=0
# Setting for bring up,
# booting from SRAM
CFG_BYPASS_EMI :=0
#Pull Hi Flash enable bit for UART META
CFG_ENABLE_GPIO_CHK_POINT_WITH_UART_META :=0
CFG_EVB_PLATFORM :=0
CFG_BATTERY_DETECT :=1
CFG_HIGH_BATTERY_VOLTAGE_SUPPORT :=0
CFG_UART_TOOL_HANDSHAKE :=1
CFG_USB_TOOL_HANDSHAKE :=1
CFG_USB_DOWNLOAD :=1
CFG_LOG_BAUDRATE :=921600
CFG_META_BAUDRATE :=115200
CFG_UART_LOG :=UART2
CFG_UART_META :=UART2
#CFG_UART_LOG :=UART1 ->20220515
#CFG_UART_META :=UART1
#only enable in eng mode
ifeq ("$(TARGET_BUILD_VARIANT)","eng")
CFG_OUTPUT_PL_LOG_TO_UART1:=0
CFG_FUNCTION_TRACER_SUPPORT :=0
else
CFG_OUTPUT_PL_LOG_TO_UART1:=0
CFG_FUNCTION_TRACER_SUPPORT :=0
endif
CFG_EMERGENCY_DL_SUPPORT :=1
CFG_EMERGENCY_DL_TIMEOUT_MS :=1000*5
CFG_EMERGENCY_MAX_TIMEOUT_MS :=1000*0x3fff
CFG_USBIF_COMPLIANCE :=0
CFG_MMC_ADDR_TRANS :=1
CFG_LEGACY_USB_DOWNLOAD :=0
CFG_USB_UART_SWITCH := 0
CFG_HW_WATCHDOG :=1
CFG_BOOT_ARGUMENT :=1
CFG_BOOT_ARGUMENT_BY_ATAG := 1
CFG_RAM_CONSOLE :=1
CFG_MTJTAG_SWITCH :=0
CFG_MDMETA_DETECT :=0
CFG_APWDT_DISABLE :=0
CFG_MDWDT_DISABLE :=0
CFG_SYS_STACK_SZ :=3*1024
CFG_WORLD_PHONE_SUPPORT :=1
KPD_USE_EXTEND_TYPE := 0
ONEKEY_REBOOT_NORMAL_MODE_PL :=1
KPD_PMIC_LPRST_TD :=1
MTK_PMIC_RST_KEY :=
CFG_USB_AUTO_DETECT :=0
CFG_USB_AUTO_DETECT_TIMEOUT_MS :=1000*3
CFG_FEATURE_ENCODE :=v1
FEATURE_DOWNLOAD_SCREEN :=0
MTK_EFUSE_WRITER_SUPPORT :=no
DIAG_COMPOSITE_PRELOADER :=0
CONFIG_MTK_USB_UNIQUE_SERIAL :=0
###################################################################
# image loading options
###################################################################
#For Normal Boot
CFG_LOAD_UBOOT :=1
#For Dummy AP
CFG_LOAD_MD_ROM :=0
CFG_LOAD_MD_RAMDISK :=0
CFG_LOAD_MD_DSP :=0
CFG_LOAD_MD3_ROM :=0
#For SLT and Dummy AP
CFG_LOAD_AP_ROM :=0
#For CTP
CFG_LOAD_CONN_SYS :=0
#For SLT
CFG_LOAD_SLT_MD :=0
CFG_LOAD_SLT_MD32 :=0
###################################################################
# Dummy Load address
# If image header have load address, we use address in image header
# If not, we use address here
###################################################################
#For Normal Boot
CFG_UBOOT_MEMADDR :=0x41E00000
#For Dummy AP
CFG_MD1_ROM_MEMADDR :=0x42000000
CFG_MD1_RAMDISK_MEMADDR :=0x49CC0000
CFG_MD2_ROM_MEMADDR :=0x42000000
CFG_MD2_RAMDISK_MEMADDR :=0x43400000
CFG_MD_DSP_MEMADDR :=0x4A000000
CFG_MD3_ROM_MEMADDR :=0x52000000
#For SLT and Dummy AP
CFG_AP_ROM_MEMADDR :=0x62000000
#For CTP
CFG_CONN_SYS_MEMADDR :=0x45A00000
#For SLT
CFG_TDD_MD_ROM_MEMADDR :=0x40000000
CFG_TDD_ONLY_ROM_MEMADDR :=0x41000000
CFG_FDD_MD_ROM_MEMADDR :=0x42000000
CFG_2G_MD_ROM_MEMADDR :=0x43000000
CFG_MD32P_ROM_MEMADDR :=0x44000000
CFG_MD32D_ROM_MEMADDR :=0x45002000
CFG_BOOTA64_MEMADDR :=0x40000000
CFG_DTB_MEMADDR :=0x40000300
CFG_IMAGE_AARCH64_MEMADDR :=0x40080000
#For ATF
CFG_ATF_ROM_MEMADDR :=0x43001000-0x240
CFG_BOOTIMG_HEADER_MEMADDR :=0x40010800
CFG_ATF_SUPPORT :=1
CFG_ATF_LOG_SUPPORT :=1
CFG_TEE_SUPPORT :=0
CFG_MICROTRUST_TEE_SUPPORT :=0
CFG_TRUSTONIC_TEE_SUPPORT :=0
CFG_TEE_SECURE_MEM_PROTECTED :=1
CFG_TEE_TRUSTED_APP_HEAP_SIZE := 0xA00000
CFG_GOOGLE_TRUSTY_SUPPORT :=0
#For SRAM Protection
CFG_NON_SECURE_SRAM_ADDR :=0x0010DC00
CFG_NON_SECURE_SRAM_SIZE :=0x4000
3: /home/ubuntu/Mediatek/code/trusty/vendor/mediatek/proprietary/platform/mt6735/rules.mk
#
# Copyright (C) 2015 MediaTek Inc.
#
# Modification based on code covered by the below mentioned copyright
# and/or permission notice(S).
#
#
# Copyright (c) 2015, Google, Inc. All rights reserved
#
# Permission is hereby granted, free of charge, to any person obtaining
# a copy of this software and associated documentation files
# (the "Software"), to deal in the Software without restriction,
# including without limitation the rights to use, copy, modify, merge,
# publish, distribute, sublicense, and/or sell copies of the Software,
# and to permit persons to whom the Software is furnished to do so,
# subject to the following conditions:
#
# The above copyright notice and this permission notice shall be
# included in all copies or substantial portions of the Software.
#
# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
# EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
# IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
# CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
# TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
# SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#
LOCAL_DIR := $(GET_LOCAL_DIR)
MODULE := $(LOCAL_DIR)
ifeq (false,$(call TOBOOL,$(KERNEL_32BIT)))
ARCH := arm64
else
ARCH := arm
ARM_CPU := cortex-a15
endif
WITH_SMP := 1
KERNEL_BASE ?= 0x4f040000
MEMBASE ?= $(KERNEL_BASE)
MEM_SIZE ?= 0x200000
ifeq (false,$(call TOBOOL,$(KERNEL_32BIT)))
MEMSIZE ?= 1
else
MEMSIZE ?= $(MEM_SIZE)
endif
CFG_LOG_REG_BASE ?= UART1_BASE
#CFG_LOG_REG_BASE ?= UART0_BASE -> 20220515
CFG_LOG_BAUDRATE ?= 921600
GLOBAL_INCLUDES += \
$(LOCAL_DIR)/include
MODULE_SRCS += \
$(LOCAL_DIR)/debug.c \
$(LOCAL_DIR)/platform.c \
$(LOCAL_DIR)/smc.c \
$(LOCAL_DIR)/uart.c \
$(LOCAL_DIR)/gpt.c \
$(LOCAL_DIR)/reg_base.c \
MODULE_DEPS += \
dev/interrupt/arm_gic \
dev/timer/arm_generic
GLOBAL_DEFINES += \
MEMBASE=$(MEMBASE) \
MEMSIZE=$(MEMSIZE) \
MMU_WITH_TRAMPOLINE=1 \
ifeq (false,$(call TOBOOL,$(KERNEL_32BIT)))
else
GLOBAL_DEFINES += \
WITH_TIMERS_MIGRATION=1 \
UART_LOG_BAUDRATE=$(CFG_LOG_BAUDRATE) \
UART_LOG_REG_BASE=$(CFG_LOG_REG_BASE) \
DISABLE_TRACE_INIT_AFTER_BOOTUP=1 \
ifeq (eng,$(TARGET_BUILD_VARIANT))
GLOBAL_DEFINES += \
WITH_MT_TRUSTY_DEBUGFS=1 \
WITH_HWCRYPTO_UNITTEST=1
endif # TARGET_BUILD_VARIANT
endif # KERNEL_32BIT==true
LINKER_SCRIPT += \
$(BUILDDIR)/system-onesegment.ld
include make/module.mk
4：/home/ubuntu/Mediatek/code/vendor/mediatek/proprietary/bootable/bootloader/preloader/platform/mt6735/mode/DUMMY_AP.mak
HW_INIT_ONLY :=
CFG_LOAD_MD_ROM :=1
CFG_LOAD_MD_RAMDISK :=1
CFG_LOAD_AP_ROM :=1
CFG_LOAD_UBOOT :=0
CFG_LOAD_MD_DSP :=1
CFG_LOAD_MD3_ROM :=1
CFG_ATF_SUPPORT :=0
CFG_UART_LOG :=UART2
CFG_UART_META :=UART2
5：/home/ubuntu/Mediatek/code/vendor/mediatek/proprietary/bootable/bootloader/lk/platform/mt6735/uart.c
void uart_init_early(void)
{
// 20220521
#ifdef GPIO_UART_UTXD0_PIN
mt_set_gpio_mode(GPIO_UART_UTXD0_PIN, GPIO_UART_UTXD0_PIN_M_UTXD);
mt_set_gpio_dir(GPIO_UART_UTXD0_PIN, GPIO_DIR_OUT);
#endif
#ifdef GPIO_UART_URXD0_PIN
mt_set_gpio_mode(GPIO_UART_URXD0_PIN, GPIO_UART_URXD0_PIN_M_URXD);
mt_set_gpio_dir(GPIO_UART_URXD0_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_enable(GPIO_UART_URXD0_PIN, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(GPIO_UART_URXD0_PIN, GPIO_PULL_UP);
#endif
#ifdef GPIO_UART_UTXD1_PIN
mt_set_gpio_mode(GPIO_UART_UTXD1_PIN, GPIO_UART_UTXD1_PIN_M_UTXD);
mt_set_gpio_dir(GPIO_UART_UTXD1_PIN, GPIO_DIR_OUT);
#endif
#ifdef GPIO_UART_URXD1_PIN
mt_set_gpio_mode(GPIO_UART_URXD1_PIN, GPIO_UART_URXD1_PIN_M_URXD);
mt_set_gpio_dir(GPIO_UART_URXD1_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_enable(GPIO_UART_URXD1_PIN, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(GPIO_UART_URXD1_PIN, GPIO_PULL_UP);
#endif
#ifdef GPIO_UART_UTXD2_PIN
mt_set_gpio_mode(GPIO_UART_UTXD2_PIN, GPIO_UART_UTXD2_PIN_M_UTXD);
mt_set_gpio_dir(GPIO_UART_UTXD2_PIN, GPIO_DIR_OUT);
#endif
#ifdef GPIO_UART_URXD2_PIN
mt_set_gpio_mode(GPIO_UART_URXD2_PIN, GPIO_UART_URXD2_PIN_M_URXD);
mt_set_gpio_dir(GPIO_UART_URXD2_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_enable(GPIO_UART_URXD2_PIN, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(GPIO_UART_URXD2_PIN, GPIO_PULL_UP);
#endif
#ifdef GPIO_UART_UTXD3_PIN
mt_set_gpio_mode(GPIO_UART_UTXD3_PIN, GPIO_UART_UTXD3_PIN_M_UTXD);
mt_set_gpio_dir(GPIO_UART_UTXD3_PIN, GPIO_DIR_OUT);
#endif
#ifdef GPIO_UART_URXD3_PIN
mt_set_gpio_mode(GPIO_UART_URXD3_PIN, GPIO_UART_URXD3_PIN_M_URXD);
mt_set_gpio_dir(GPIO_UART_URXD3_PIN, GPIO_DIR_IN);
mt_set_gpio_pull_enable(GPIO_UART_URXD3_PIN, GPIO_PULL_ENABLE);
mt_set_gpio_pull_select(GPIO_UART_URXD3_PIN, GPIO_PULL_UP);
#endif
#ifdef __ENABLE_UART_LOG_SWITCH_FEATURE__
if(get_uart_port_id() == 1){
mtk_set_current_uart(UART1);
mtk_uart_power_on(UART1);
}else if(get_uart_port_id() == 2){
mtk_set_current_uart(UART2);
mtk_uart_power_on(UART2);
}else if(get_uart_port_id() == 3){
mtk_set_current_uart(UART3);
mtk_uart_power_on(UART3);
}else if(get_uart_port_id() == 4){
mtk_set_current_uart(UART4);
mtk_uart_power_on(UART4);
}
#ifndef CONFIG_DENALI_2
else if(get_uart_port_id() == 5){
mtk_set_current_uart(UART5);
mtk_uart_power_on(UART5);
}
#endif
else {
mtk_set_current_uart(UART4);
mtk_uart_power_on(UART4);
}
#else
mtk_set_current_uart(UART1);
mtk_uart_power_on(UART1);
#endif
DRV_SetReg32(UART_FCR(g_uart), UART_FCR_FIFO_INIT); /* clear fifo */
mt65xx_reg_sync_writew(UART_NONE_PARITY | UART_WLS_8 | UART_1_STOP, UART_LCR(g_uart));
g_brg = CONFIG_BAUDRATE;
uart_setbrg();
}6：/home/ubuntu/Mediatek/code/orangepi/projects/IoT/IoT_mt6737m/IoT_bd6737m_35g_b_m0_op_smt_hd720_pcb_v2/code/kernel-3.18/arch/arm/boot/dts/mt6735m.dtsi
/* chosen */
chosen {
bootargs = "console=tty0 console=ttyMT1,921600n1 root=/dev/ram \
initrd=0x44000000,0x1000000 loglevel=8 androidboot.hardware=mt6735";
};7：/home/ubuntu/Mediatek/code/orangepi/projects/IoT/IoT_mt6737m/IoT_bd6737m_35g_b_m0_op_smt_hd720_pcb_v2/code/kernel-3.18/arch/arm/configs/bd6737m_35g_b_m0_debug_defconfig
#
# Boot options
#
CONFIG_USE_OF=y
CONFIG_ATAGS=y
# CONFIG_DEPRECATED_PARAM_STRUCT is not set
CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE=y
CONFIG_BUILD_ARM_APPENDED_DTB_IMAGE_NAMES="bd6737m_35g_b_m0"
CONFIG_ZBOOT_ROM_TEXT=0
CONFIG_ZBOOT_ROM_BSS=0
# CONFIG_ARM_APPENDED_DTB is not set
CONFIG_CMDLINE="console=tty0 console=ttyMT1,921600n1 root=/dev/ram vmalloc=496M slub_max_order=0 slub_debug=O "
CONFIG_CMDLINE_FROM_BOOTLOADER=y
# CONFIG_CMDLINE_EXTEND is not set
# CONFIG_CMDLINE_FORCE is not set
# CONFIG_XIP_KERNEL is not set
# CONFIG_KEXEC is not set
# CONFIG_CRASH_DUMP is not set
CONFIG_AUTO_ZRELADDR=y
三、烧录Android Image
拔掉跳线冒J5，运行sudo ./flash_tool，打开Flash Tool，找到对应的scatter文件，先选择firmware upgrade，然后点击Download 按钮，然后插上micro usb线，就可以下载Android镜像进行烧录了。
拔掉USB烧录线，然后按下powerkey开启电源
[PLFM] USB cable in
[pmic_IsUsbCableIn] 1
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Release
[pmic_IsUsbCableIn] 1
pl pmic powerkey Press
[LIB] NS-CHIP
GCPU Enhance,V1.0
[TZ_INIT] tee_verify_image : passed
[BLDR] bldr load tee part ret=0x0, addr=0x43001000
[BLDR] part_load_raw_part ret=0x0
[BLDR] part_load_images ret=0x0
ignore bat check
[PLFM] boot to LK by ATAG.
boot reason: 1
boot mode: 0
META COM0: 0
boot uart: 0x11003000
boot uart_baudrate: 921600
boot uart_enable: 1
rank[0] size: 0x3FFC0000
tee reserved mem: 0x000000007FFC0000, 0x0000000000040000
md_type[0]: 0x0
md_type[1]: 0x0
boot time: 8540
DDR reserve mode: enable = 0, success = 0
dram buffer size: 1688768
SMC: 0x0
LK: 0x6
KERNEL: 0x6
NONSEC SRAM Addr: 0x10DC00
NONSEC SRAM Size: 0x4000
DTB Addr: 0x0
DTB Size: 0x0
PL_VERSION = 0.1.00
[TZ_INIT] atf_log_port : 0x11003000
[TZ_INIT] atf_log_baudrate : 0xE1000
[TZ_INIT] atf_irq_num : 281
[TZ_INIT] ATF log buffer start : 0x7FFC0000
[TZ_INIT] ATF log buffer size : 0x40000
[TZ_INIT] ATF aee buffer start : 0x7FFFC000
[TZ_INIT] ATF aee buffer size : 0x4000
[BLDR] Others, jump to ATF
[BLDR] jump to 0x41E00000
[BLDR] <0x41E00000>=0xEA000007
[BLDR] <0x41E00004>=0xEA007460
[TZ_SEC_CFG] SRAMROM Secure Addr 0xDC00
[TZ_SEC_CFG] SRAMROM Secure Control 0x0
[TZ_SEC_CFG] SRAMROM Secure Control 0xB69
[TZ_SEC_CFG] SRAMROM Secure Control 0x1B680B69
[TZ_INIT] ATF entry addr, aligned addr : 0x43001000, 0x43000000
[TZ_EMI_MPU] MPU [0x43000000-0x4302FFFF]
[TZ_INIT] set secure memory protection : 0x43000000, 0x4302FFFF (1)
[TZ_INIT] Jump to ATF, then 0x41E00000
[ATF][ 0.000000]BL33 boot argument location=0x4219c480
[ATF][ 0.000000]BL33 boot argument size=0x170
[ATF][ 0.000000]BL33 start addr=0x41e00000
[ATF][ 0.000000]teearg addr=0x101000
[ATF][ 0.000000]atf_magic=0x4d415446
[ATF][ 0.000000]tee_support=0x0
[ATF][ 0.000000]tee_entry=0x0
[ATF][ 0.000000]tee_boot_arg_addr=0x101100
[ATF][ 0.000000]atf_log_port=0x11003000
[ATF][ 0.000000]atf_log_baudrate=0xe1000
[ATF][ 0.000000]atf_log_buf_start=0x7ffc0000
[ATF][ 0.000000]atf_log_buf_size=0x40000
[ATF][ 0.000000]atf_aee_debug_buf_start=0x7fffc000
[ATF][ 0.000000]atf_aee_debug_buf_size=0x4000
[ATF][ 0.000000]atf_irq_num=281
[ATF][ 0.000000]BL33_START_ADDRESS=0x41e00000
[ATF][ 0.000000]atf chip_code[335]
[ATF][ 0.000000]atf chip_ver[0]
[ATF][ 0.000000]###@@@ MP0_MISC_CONFIG3:0x00000000 @@@###
[ATF][ 0.000000]###@@@ MP0_MISC_CONFIG3:0x0000e000 @@@###
[ATF][ 0.000000]mmap atf buffer : 0x7ffc0000, 0x40000
[ATF][ 0.000000]mmap atf buffer (force 2MB aligned): 0x7fe00000, 0x200000
NOTICE: BL3-1: v1.0(debug):
NOTICE: BL3-1: Built : 18:10:55, May 21 2022
[ATF][ 0.000000]sta=0x0 int=0xffc
[ATF][ 0.000000]is_power_on_boot: true
[ATF][ 0.000000]mt_log_setup - atf_buf_addr : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_buf_size : 0x2bf00
[ATF][ 0.000000]mt_log_setup - atf_write_pos : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_read_pos : 0x7ffc0100
[ATF][ 0.000000]mt_log_setup - atf_buf_lock : 0x0
[ATF][ 0.000000]mt_log_setup - mt_log_buf_end : 0x7ffebfff
[ATF][ 0.000000]mt_log_setup - ATF_CRASH_LAST_LOG_SIZE : 0x8000
[ATF][ 0.000000]mt_log_setup - ATF_EXCEPT_BUF_SIZE_PER_CPU : 0x1000
[ATF][ 0.000000]mt_log_setup - ATF_EXCEPT_BUF_SIZE : 0x8000
[ATF][ 0.000000]mt_log_setup - PLATFORM_CORE_COUNT : 0x8
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[0]: 0x7fff4000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[1]: 0x7fff5000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[2]: 0x7fff6000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[3]: 0x7fff7000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[4]: 0x7fff8000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[5]: 0x7fff9000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[6]: 0x7fffa000
[ATF][ 0.000000]mt_log_setup - atf_except_write_pos_per_cpu[7]: 0x7fffb000
[ATF][ 0.000000]mt_log_setup - atf_crash_flag : 0x0
[ATF][ 0.000000]mt_log_setup - atf_crash_log_addr : 0x0
[ATF][ 0.000000]mt_log_setup - atf_crash_log_size : 0x0
[ATF][ 0.000000]ATF log service is registered (0x7ffc0000, aee:0x7fffc000)
[ATF][ 0.000000]BL3-1: v1.0(debug):
[ATF][ 0.000000]BL3-1: Built : 18:10:55, May 21 2022
INFO: BL3-1: Initializing runtime services
[ATF][ 0.000000][BL31] Jump to FIQD for initialization!
INFO: BL3-1: Preparing for EL3 exit to normal world, LK
INFO: BL3-1: Next image address = 0x41e00000
INFO: BL3-1: Next image spsr = 0x1d3
[ATF][ 0.000000][BL31] Final dump!
[0] [WDT] mtk_wdt_mode LK config mode value=5d
[0] [WDT] mtk_wdt_mode_config LK mode value=10, tmp:22000010
[0] [WDT] UB wdt init
[0] [WDT] mtk_wdt_mode LK config mode value=10
[0] [WDT] mtk_wdt_mode_config LK mode value=5d, tmp:2200005d
[0] WDT NONRST=0x20000000
[0] [PROFILE] ------- WDT Init takes 3 ms --------
[0] [pmic_init] LK Start..................
[0] [pmic_init] MT6325 CHIP Code = 0x2820
[0] [pmic_init] Done
[0] [PROFILE] ------- pmic_init takes 1 ms --------
[0] [PROFILE] ------- platform_early_init takes 8 ms --------
[0] welcome to lk
[0] calling constructors
[0] initializing heap
[0] base 0x41e7c694 size 8927596 bytes
[0] initializing threads
[0] initializing dpc
[0] initializing timers
[0] creating bootstrap completion thread
[10] top of bootstrap2()
[20] initializing platform
[20] ==LK info ==
[20] Build time:May 21 2022, 18:27:19
[20] chip_code[0x335]
[20] chip_ver[0x0]
[20] ==LK info ==
[20] platform_init()
[20] [mmc_init]: msdc0 start mmc_init_host() in LK...
[20] [msdc_init]: msdc0 Host controller intialization start
[20] [MSDC] config VEMC to 3V in lk
[20] [SD0] Pins mode(1), none(0), down(1), up(2), keep(3)
[20] [SD0] Pins mode(2), none(0), down(1), up(2), keep(3)
[20] [MSDC] config VEMC to 3V in lk
[20] [info][msdc_set_startbit 1248] read data start bit at rising edge
[20] [info][msdc_config_clksrc] input clock is 400000kHz
[20] [SD0] Bus Width: 1
[20] [info][msdc_config_clksrc] input clock is 400000kHz
[20] [info][msdc_set_startbit 1248] read data start bit at rising edge
[20] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0)
[20] [msdc_init]: msdc0 Host controller intialization done
[40] [mmc_init]: msdc0 start mmc_init_card()in LK...
[40] [mmc_init_card]: start
[140] [info][msdc_config_clksrc] input clock is 400000kHz
[140] [info][msdc_set_startbit 1248] read data start bit at rising edge
[140] [SD0] SET_CLK(260kHz): SCLK(259kHz) MODE(0) DDR(0) DIV(385) DS(0) RS(0)
[160] [SD0] Bus Width: 8
[160] [SD0] Switch to High-Speed mode!
[160] [SD0] Size: 7456 MB, Max.Speed: 52000 kHz, blklen(512), nblks(15269888), ro(0)
[160] [mmc_init_mem_card 3240][SD0] Initialized, eMMC50
[160] before host->cur_bus_clk(259740)
[160] [info][msdc_config_clksrc] input clock is 400000kHz
[160] [info][msdc_set_startbit 1248] read data start bit at rising edge
[180] [SD0] SET_CLK(52000kHz): SCLK(50000kHz) MODE(0) DDR(0) DIV(2) DS(0) RS(0)
[180] host->cur_bus_clk(50000000)
[180] [mmc_init_card]: finish successfully
[180] [mt_part_register_device]
[180] [GPT_LK]Parsing Primary GPT now...
[180] [GPT_LK][0]name=proinfo, part_id=8, start_sect=0x400, nr_sects=0x1800
[180] [GPT_LK][1]name=nvram, part_id=8, start_sect=0x1c00, nr_sects=0x2800
[180] [GPT_LK][2]name=protect1, part_id=8, start_sect=0x4400, nr_sects=0x5000
[180] [GPT_LK][3]name=protect2, part_id=8, start_sect=0x9400, nr_sects=0x5000
[180] [GPT_LK][4]name=lk, part_id=8, start_sect=0xe400, nr_sects=0x400
[180] [GPT_LK][5]name=para, part_id=8, start_sect=0xe800, nr_sects=0x400
[180] [GPT_LK][6]name=boot, part_id=8, start_sect=0xec00, nr_sects=0x8000
[200] [GPT_LK][7]name=recovery, part_id=8, start_sect=0x16c00, nr_sects=0x8000
[200] [GPT_LK][8]name=logo, part_id=8, start_sect=0x1ec00, nr_sects=0x4000
[200] [GPT_LK][9]name=expdb, part_id=8, start_sect=0x22c00, nr_sects=0x5000
[200] [GPT_LK][10]name=seccfg, part_id=8, start_sect=0x27c00, nr_sects=0x400
[200] [GPT_LK][11]name=oemkeystore, part_id=8, start_sect=0x28000, nr_sects=0x1000
[200] [GPT_LK][12]name=secro, part_id=8, start_sect=0x29000, nr_sects=0x3000
[200] [GPT_LK][13]name=keystore, part_id=8, start_sect=0x2c000, nr_sects=0x4000
[200] [GPT_LK][14]name=tee1, part_id=8, start_sect=0x30000, nr_sects=0x2800
[200] [GPT_LK][15]name=tee2, part_id=8, start_sect=0x32800, nr_sects=0x2800
[200] [GPT_LK][16]name=frp, part_id=8, start_sect=0x35000, nr_sects=0x800
[200] [GPT_LK][17]name=nvdata, part_id=8, start_sect=0x35800, nr_sects=0x10000
[200] [GPT_LK][18]name=metadata, part_id=8, start_sect=0x45800, nr_sects=0x12800
[220] [GPT_LK][19]name=system, part_id=8, start_sect=0x58000, nr_sects=0x300000
[220] [GPT_LK][20]name=cache, part_id=8, start_sect=0x358000, nr_sects=0xc8000
[220] [GPT_LK][21]name=userdata, part_id=8, start_sect=0x420000, nr_sects=0xa67c00
[220] [GPT_LK][22]name=flashinfo, part_id=8, start_sect=0xe87c00, nr_sects=0x8000
[220] [GPT_LK]Success to find valid GPT.
[220] [SD0] boot device found
[220] [PROFILE] ------- NAND/EMMC init takes 104 ms --------
[220] [PART_LK][get_part] boot
[220] [LK_BOOT] Load '<null>' partition to 0x45000000 (608 bytes in 1 ms)
[220] [PART_LK][get_part] boot
[540] [LK_BOOT] Load '<null>' partition to 0x45000000 (7256064 bytes in 159 ms)
[540] Kernel(0) zimage_addr:0x45000800(6dadb8),dtb_addr:0x456db5b8(fb2a)
[540] Copy DTB from 0x456db5b8 to 0x4e000000(fb2a)
[540] [LK] fdt setup addr:0x4e000000 status:1!!!
[540] [LEDS]LK: leds_init: mt65xx_backlight_off
[540] [LEDS]LK: mt65xx_backlight_off
[540] [LEDS]LK: lcd-backlight level is 0
[540] [LK_DDP/INFO]enable pwm0 clk, CG0 0xffffffff, CG1 0xfffffffc, dummy CON = 0x0
[540] [LK_DDP/PWM][PWM] set reg[0x102100b0] = 0x00000000
[540] [LK_DDP/PWM][PWM] disp_pwm_init : CLK_CFG_7 0x0 => 0x0
[560] [LK_DDP/PWM][PWM] disp_pwm_init : PWM config data (0,0)
[560] [LK_DDP/PWM][PWM] set reg[0x1100e010] = 0x00000000
[560] [LK_DDP/PWM][PWM] set reg[0x1100e014] = 0x000003ff
[560] [LK_DDP/PWM][PWM] disp_pwm_set_backlight(id = 0x1, level_1024 = 0)
[560] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000000
[560] [LK_DDP/PWM][PWM] set reg[0x1100e014] = 0x000003ff
[560] [LK_DDP/PWM][PWM] set reg[0x1100e000] = 0x00000000
[560] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000001
[560] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e000] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e004] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e008] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e00c] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e010] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e014] = 0x00000000
[560] [LK_DDP/PWM][PWM] reg[0x1100e018] = 0x00000000
[580] [LK_DDP/PWM][PWM] reg[0x1100e01c] = 0x00000000
[580] [LK_DDP/PWM][PWM] reg[0x1100e020] = 0x00000000
[580] [LK_DDP/PWM][PWM] reg[0x1100e024] = 0x00000000
[580] [LK_DDP/PWM][PWM] reg[0x1100e028] = 0x00000000
[580] [PROFILE] ------- led init takes 16 ms --------
[580] [upmu_is_chr_det] 1
[580] [PART_LK][get_part] para
[LK_ENV]ENV SIG Wrong
[LK_ENV]no valid env
[580] [PROFILE] ------- ENV init takes 2 ms --------
[580] [DISP]func|disp_lcm_probe
[580] [DISP]we will check lcm: ili9881c_hd720_dsi_vdo_cpt
[580] [DISP]func|_display_interface_path_init
[580] [LK_DDP/ddp_manager]scenario display_interface acquire mutex 0 , left mutex 0x1e!
[580] [LK_DDP/ddp_manager]assign default irqs table index 0
[580] [LK_DDP/ddp_manager]create handle 0x41e69f40 on scenario display_interface
[600] [LK_DDP/ddp_manager] scenario display_interface include module ovl0
[600] [LK_DDP/ddp_manager] scenario display_interface include module color0
[600] [LK_DDP/ddp_manager] scenario display_interface include module ccorr
[600] [LK_DDP/ddp_manager] scenario display_interface include module aal
[600] [LK_DDP/ddp_manager] scenario display_interface include module gamma
[600] [LK_DDP/ddp_manager] scenario display_interface include module dither
[600] [LK_DDP/ddp_manager] scenario display_interface include module rdma0
[600] [LK_DDP/ddp_manager] scenario display_interface include module pwm0
[600] [LK_DDP/ddp_manager] scenario display_interface include module dsi0
[600] [DISPCHECK]dpmgr create path SUCCESS(0x41e69f40)
[600] [LK_DDP/ddp_manager]set dst module on scenario display_interface, module dsi0
[600] [LK_DDP/ddp_path]ddp_set_dst_module, scenario=display_interface, dst_module=dsi0
[620] [LK_DDP/ddp_path]dsi0 is already on path
[620] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[620] [LK_DDP/ddp_manager]path set lcm drv handle 0x41e69f40
[620] [LK_DDP/ddp_manager]dsi0 set lcm utils
[620] [LK_DDP/ddp_manager]path init on scenario display_interface
[620] [LK_DDP/ddp_path]ddp path m4u off
[620] [LK_DDP/ddp_path]ddp path top clock on
[620] [LK_DDP/INFO]enable smi clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[620] [LK_DDP/INFO]enable mutex clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[620] [LK_DDP/ddp_path]ddp CG:fffffffc
[620] [LK_DDP/ddp_path]mutex sof: dsi0 dst module dsi0 :vido_mode
[620] [LK_DDP/ddp_path]module ovl0 added to mutex 0
[620] [LK_DDP/ddp_path]module color0 added to mutex 0
[620] [LK_DDP/ddp_path]module ccorr added to mutex 0
[620] [LK_DDP/ddp_path]module aal added to mutex 0
[640] [LK_DDP/ddp_path]module gamma added to mutex 0
[640] [LK_DDP/ddp_path]module dither added to mutex 0
[640] [LK_DDP/ddp_path]module rdma0 added to mutex 0
[640] [LK_DDP/ddp_path]module pwm0 added to mutex 0
[640] [LK_DDP/ddp_path]mutex 0 value=0x2f940, sof=dsi0
[640] [LK_DDP/ddp_path]path connect on scenario display_interface
[640] [LK_DDP/ddp_path]connect_path: ovl0 to dsi0
[640] [LK_DDP/ddp_path]connect mout ovl0 to color0 value 0x1
[640] [LK_DDP/ddp_path]connect mout dither to rdma0 value 0x1
[640] [LK_DDP/ddp_path]connect out_s rdma0 to dsi0 , bits=0x2
[640] [LK_DDP/ddp_path]connect in_s ovl0 to color0 , bits=0x1
[640] [LK_DDP/ddp_path]connect in_s rdma0 to dsi0 , bits=0x1
[640] [LK_DDP/ddp_manager]scenario display_interface init module ovl0
[640] [LK_DDP/INFO]enable ovl0 clk, CG0 0xfffffbfc, CG1 0xfffffffc, dummy CON = 0xfffffbfc
[640] [LK_DDP/OVL]OVL0Init open CG 0xfffffbfc
[660] [LK_DDP/ddp_manager]scenario display_interface init module color0
[660] [LK_DDP/INFO]enable color0 clk, CG0 0xffffbbfc, CG1 0xfffffffc, dummy CON = 0xffffbbfc
[660] [LK_DDP/ddp_manager]scenario display_interface init module aal
[660] [LK_DDP/INFO]enable aal clk, CG0 0xfffebbfc, CG1 0xfffffffc, dummy CON = 0xfffebbfc
[660] [LK_DDP/ddp_manager]scenario display_interface init module gamma
[660] [LK_DDP/INFO]enable gamma clk, CG0 0xfffcbbfc, CG1 0xfffffffc, dummy CON = 0xfffcbbfc
[660] [LK_DDP/ddp_manager]scenario display_interface init module rdma0
[660] [LK_DDP/INFO]enable rdma0 clk, CG0 0xfffcb3fc, CG1 0xfffffffc, dummy CON = 0xfffcb3fc
[660] [LK_DDP/RDMA]RDMA0Init CG 0xfffcb3fc
[660] [LK_DDP/ddp_manager]scenario display_interface init module dsi0
[660] [DISP]func|ddp_dsi_init
[660] [LK_DDP/INFO]enable dsi0 clk, CG0 0xfffcb3fc, CG1 0xfffffff0, dummy CON = 0xfffcb3fc
[670] [DISPCHECK]dsi0 init finished
[680] [LK_DDP/ddp_manager]path config ovl 0, rdma 0, wdma 0, dst 1 on handle 0x41e69f40 scenario display_interface
[680] [LK_DDP/ddp_manager]scenario display_interface config module ovl0
[680] [LK_DDP/ddp_manager]scenario display_interface config module color0
[680] [LK_DDP/ddp_manager]scenario display_interface config module aal
[680] [LK_DDP/ddp_manager]scenario display_interface config module gamma
[680] [LK_DDP/ddp_manager]scenario display_interface config module dither
[680] [LK_DDP/DITHER]error:[DITHER] invalid dither bpp = 0
[680] [LK_DDP/ddp_manager]scenario display_interface config module rdma0
[680] [LK_DDP/RDMA]FIFO_VALID_Size = 0x020 = 32
[680] [LK_DDP/RDMA]ultra_low_level = 0x06b = 107
[680] [LK_DDP/RDMA]pre_ultra_low_level = 0x05f = 95
[680] [LK_DDP/RDMA]pre_ultra_high_level = 0x06b = 107
[680] [LK_DDP/RDMA]ultra_high_ofs = 0x001 = 1
[700] [LK_DDP/RDMA]pre_ultra_low_ofs = 0x0a0 = 160
[700] [LK_DDP/RDMA]pre_ultra_high_ofs = 0x001 = 1
[700] [LK_DDP/ddp_manager]scenario display_interface config module dsi0
[700] [DISP]func|ddp_dsi_config
[700] [DISPCHECK][DDPDSI] DSI Mode: BURST_VDO_MODE
[700] [DISPCHECK][DDPDSI] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[700] [DISPCHECK][DDPDSI] vact: 8, vbp: 16, vfp: 16, vact_line: 1280, hact: 10, hbp: 80, hfp: 80, hblank: 0
[700] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[700] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 250, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[700] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[700] [DISP]func|DSI_PHY_clk_setting
[700] [DISP][mipitx/reg]0x14018044=0x88492481
[700] [DISP][mipitx/reg]0x14018044=0x88492483
[720] [DISP][mipitx/reg]0x14018040=0x00000082
[720] [DISP][mipitx/reg]0x14018000=0x00000402
[720] [DISP][mipitx/reg]0x14018000=0x00000403
[720] [DISP][mipitx/reg]0x14018068=0x00000003
[720] [DISP][mipitx/reg]0x14018068=0x00000101
[720] [DISP][mipitx/reg]0x14018050=0x00000000
[720] [DISP][mipitx/reg]0x14018050=0x00000000
[720] [DISP][mipitx/reg]0x14018050=0x00000000
[720] [DISP][mipitx/reg]0x14018054=0x00000003
[720] [DISP][mipitx/reg]0x14018058=0x26000000
[720] [DISP][mipitx/reg]0x14018058=0x26760000
[720] [DISP][mipitx/reg]0x14018058=0x26762700
[720] [DISP][mipitx/reg]0x14018058=0x26762762
[720] [DISP][mipitx/reg]0x14018054=0x00000003
[720] [DISP][mipitx/reg]0x14018054=0x01b10003
[720] [DISP][mipitx/reg]0x1401805c=0x048b0000
[720] [DISP][mipitx/reg]0x1401805c=0x048b048b
[720] [DISP][dsi_drv.c] PLL config:data_rate=500,txdiv=1,pcw=645277538,delta1=5,pdelta1=0x48b
[720] [DISP][mipitx/reg]0x14018054=0x01b10007
[740] [DISP][mipitx/reg]0x14018004=0x00000821
[740] [DISP][mipitx/reg]0x14018008=0x00000401
[740] [DISP][mipitx/reg]0x1401800c=0x00000101
[740] [DISP][mipitx/reg]0x14018010=0x00000101
[740] [DISP][mipitx/reg]0x14018014=0x00000101
[740] [DISP][mipitx/reg]0x14018050=0x00000001
[740] [DISP][mipitx/reg]0x14018060=0x00000000
[740] [DISP][mipitx/reg]0x14018060=0x00000001
[740] [DISP][mipitx/reg]0x14018040=0x00000082
[740] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 17(ns), Unit Interval = 3(ns). , lane# = 4
[740] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 120, HS_ZERO = 9, HS_PRPR = 4, LPX = 4, TA_GET = 20, TA_SURE = 6, TA_GO = 16, CLK_TRAIL = 6, CLK_ZERO = 23, CLK_HS_PRPR = 3
[740] DSI_PHY_TIMCONFIG, 0x78090404,0x08140610,0x06170100,0x00080e03
[1100] [DISP]func|DSI_set_cmdq
[1100] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[1100] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0000 : 0x00063902
[1100] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0004 : 0x8198ffff
[1100] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0008 : 0x00000104
[1120] [DISP]func|DSI_set_cmdq
[1120] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[1140] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0000 : 0x00033700
[1140] [DISP]func|DSI_dcs_read_lcm_reg_v2
[1140] DISP/ Start polling DSI read ready!!!
[1180] DISP/ Polling DSI read ready timeout!!!
[1180] DSI0 state:Waiting RX-read data
[1180] DSI Mode: lane num: transfer count: status: [1180] ---------- Start dump DSI0 registers ----------
[1180] DSI+0000 : 0x00000001 0x00000000 0x00000000 0x80000000
[1180] DSI+0010 : 0x00000000 0x00000000 0x0000007c 0x00030870
[1180] DSI+0020 : 0x00000008 0x00000010 0x00000010 0x00000500
[1180] DSI+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[1180] DSI+0040 : 0x00000000 0x00000000 0x00000000 0x00000000
[1180] DSI+0050 : 0x0000001c 0x00000104 0x000000e4 0x00000000
[1180] DSI+0060 : 0x00000001 0x00010000 0x00000000 0x00000000
[1180] DSI+0070 : 0x00000000 0x00000000 0x00000000 0x00000000
[1180] DSI+0080 : 0x00000000 0x00000000 0x00000020 0x00000000
[1190] DSI+0090 : 0x0000003c 0x00000000 0x00000000 0x00000000
[1200] DSI+00a0 : 0x00060080 0x00002000 0x00000000 0x00000000
[1200] DSI+00b0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1200] DSI+00c0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1200] DSI+00d0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1200] DSI+00e0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1200] DSI+00f0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1200] DSI+0100 : 0x00000055 0x00000000 0x00000000 0x000000b8
[1200] DSI+0110 : 0x78090404 0x08140610 0x06170100 0x00080e03
[1200] DSI+0120 : 0x00000000 0x00000000 0x00000000 0x00000000
[1200] DSI+0130 : 0x00000021 0x00000000 0x00000000 0x00000000
[1200] DSI+0140 : 0x00000000 0x00000000 0x00010001 0x01010100
[1200] DSI+0150 : 0x01080001 0x01010101 0x00000101 0x10000000
[1200] DSI+0160 : 0x00010200 0x00000001 0x00000000 0x00000000
[1210] DSI+0170 : 0x00000000 0xfff00000 0x00000000 0x00200000
[1220] DSI_CMD+0000 : 0x00000604 0x8198ffff 0x00000104 0x65c96dc6
[1220] DSI_CMD+0010 : 0x1fb52006 0x60160a3e 0xd9e50d77 0x5c42a90f
[1220] DSI_CMD+0020 : 0x787b9491 0x28f55582 0x10657df7 0xe3f39022
[1220] DSI_CMD+0030 : 0x2838feb6 0x9cb8d0d0 0x69527205 0xf6b5d582
[1220] DSI_CMD+0040 : 0xa2ee65c0 0xd474745e 0x11cfefd0 0xd1d41e17
[1220] DSI_CMD+0050 : 0x705d471d 0x57491712 0x5fc7505e 0xd27597c7
[1220] DSI_CMD+0060 : 0x5af0125b 0x5f53104f 0xd51b97fb 0x8e2651ad
[1220] DSI_CMD+0070 : 0xd736f643 0x8124585e 0x1f52c105 0xdd949d95
[1220] DSI_CMD+0080 : 0x4712c353 0xc6800d11 0x84554fb7 0xebd45444
[1220] DSI_CMD+0090 : 0x4b067445 0x84751146 0x733f15bd 0x19936d6f
[1220] DSI_CMD+00a0 : 0xb3530de1 0x0d17e508 0x4a246d30 0x6551df1c
[1220] DSI_CMD+00b0 : 0x42686bd1 0xf9287cf8 0xd37f0991 0xdacd707a
[1220] DSI_CMD+00c0 : 0x9cdb8955 0x1f82e1ce 0x20f0f876 0xbb17fd0e
[1240] DSI_CMD+00d0 : 0x533b98ba 0x04535bdc 0xe79a65ff 0x3421dbb1
[1240] DSI_CMD+00e0 : 0xefb40d55 0x1cdde64f 0x3f575591 0x521bd001
[1240] DSI_CMD+00f0 : 0x232d15d5 0x45572548 0xa4c47f4d 0x14749f66
[1240] DSI_CMD+0100 : 0x735f78cf 0x44fb44e5 0x57ec5513 0xf96a4dd8
[1240] DSI_CMD+0110 : 0xb8411748 0x79754808 0xae674c55 0x77d36f37
[1240] DSI_CMD+0120 : 0x91711452 0x559d6c32 0x96cc3dad 0x039aa1d2
[1240] DSI_CMD+0130 : 0x557d7205 0x8edd7656 0x278375e5 0xcd5fd157
[1240] DSI_CMD+0140 : 0x575cd67d 0xdc3c4919 0xe1d93340 0x9169999b
[1240] DSI_CMD+0150 : 0x419ed5d8 0xf26fcd50 0x73f50cc1 0xa8096178
[1240] DSI_CMD+0160 : 0xa6735b55 0x42d93d56 0x71d674db 0xbcd18bfd
[1240] DSI_CMD+0170 : 0xc7f817c8 0x5d75c925 0xf6b59901 0xd33735b9
[1240] DSI_CMD+0180 : 0xb55dd961 0x371417e8 0xd9596103 0x9e6bf1f1
[1240] DSI_CMD+0190 : 0x14d91fd5 0x08c30938 0x55478378 0x4eb22503
[1260] DSI_CMD+01a0 : 0xdd572651 0x179d3d1f 0xfbd09750 0xdfbf9407
[1260] DSI_CMD+01b0 : 0x92d1e931 0x9ad8cf8b 0x94e0e442 0x9a79b5d5
[1260] DSI_CMD+01c0 : 0x45a4f911 0xa5a53535 0x6031c351 0x57967a81
[1260] DSI_CMD+01d0 : 0x1b172371 0x142c5772 0x08097093 0xb198451c
[1260] DSI_CMD+01e0 : 0x5dd3c66e 0x43966fd5 0x50047605 0xf3477857
[1260] DSI_CMD+01f0 : 0x4cb1d7e7 0xf7312d59 0xa7f44f01 0xf2104578
[1260] DSI_PHY+0000 : 0x00000403 0x00000821 0x00000401 0x00000101
[1260] DSI_PHY+0010 : 0x00000101 0x00000101 0x00000000 0x00000000
[1260] DSI_PHY+0020 : 0x00000000 0x00000000 0x00000000 0x00000000
[1260] DSI_PHY+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[1260] DSI_PHY+0040 : 0x00000082 0x88492483 0x00000000 0x00000000
[1260] DSI_PHY+0050 : 0x00000001 0x01b10007 0x26762762 0x048b048b
[1260] DSI_PHY+0060 : 0x00000001 0x00000020 0x00000101 0x00000000
[1280] DSI_PHY+0070 : 0x00000000 0x00000000 0x00000000 0x00043210
[1280] DSI_PHY+0080 : 0x00000000 0x00000000 0x00000000 0x00000000
[1280] DSI_PHY+0090 : 0x00000000 0x00000000 0x00000000 0x00000000
[1280] [DISP]func|DSI_dcs_read_lcm_reg_v2
[1280] DISP/ Start polling DSI read ready!!!
[1320] DISP/ Polling DSI read ready timeout!!!
[1320] DSI0 state:Waiting RX-read data
[1320] DSI Mode: lane num: transfer count: status: [1320] ---------- Start dump DSI0 registers ----------
[1320] DSI+0000 : 0x00000001 0x00000000 0x00000000 0x80000000
[1320] DSI+0010 : 0x00000000 0x00000000 0x0000007c 0x00030870
[1320] DSI+0020 : 0x00000008 0x00000010 0x00000010 0x00000500
[1320] DSI+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[1320] DSI+0040 : 0x00000000 0x00000000 0x00000000 0x00000000
[1320] DSI+0050 : 0x0000001c 0x00000104 0x000000e4 0x00000000
[1320] DSI+0060 : 0x00000001 0x00010000 0x00000000 0x00000000
[1340] DSI+0070 : 0x00000000 0x00000000 0x00000000 0x00000000
[1340] DSI+0080 : 0x00000000 0x00000000 0x00000020 0x00000000
[1340] DSI+0090 : 0x0000003c 0x00000000 0x00000000 0x00000000
[1340] DSI+00a0 : 0x00060080 0x00002000 0x00000000 0x00000000
[1340] DSI+00b0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1340] DSI+00c0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1340] DSI+00d0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1340] DSI+00e0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1340] DSI+00f0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1340] DSI+0100 : 0x00000055 0x00000000 0x00000000 0x000000b8
[1340] DSI+0110 : 0x78090404 0x08140610 0x06170100 0x00080e03
[1340] DSI+0120 : 0x00000000 0x00000000 0x00000000 0x00000000
[1340] DSI+0130 : 0x00000021 0x00000000 0x00000000 0x00000000
[1340] DSI+0140 : 0x00000000 0x00000000 0x00010001 0x01010100
[1360] DSI+0150 : 0x01080001 0x01010101 0x00000101 0x10000000
[1360] DSI+0160 : 0x00010200 0x00000001 0x00000000 0x00000000
[1360] DSI+0170 : 0x00000000 0xfff00000 0x00000000 0x00200000
[1360] DSI_CMD+0000 : 0x00010604 0x8198ffff 0x00000104 0x65c96dc6
[1360] DSI_CMD+0010 : 0x1fb52006 0x60160a3e 0xd9e50d77 0x5c42a90f
[1360] DSI_CMD+0020 : 0x787b9491 0x28f55582 0x10657df7 0xe3f39022
[1360] DSI_CMD+0030 : 0x2838feb6 0x9cb8d0d0 0x69527205 0xf6b5d582
[1360] DSI_CMD+0040 : 0xa2ee65c0 0xd474745e 0x11cfefd0 0xd1d41e17
[1360] DSI_CMD+0050 : 0x705d471d 0x57491712 0x5fc7505e 0xd27597c7
[1360] DSI_CMD+0060 : 0x5af0125b 0x5f53104f 0xd51b97fb 0x8e2651ad
[1360] DSI_CMD+0070 : 0xd736f643 0x8124585e 0x1f52c105 0xdd949d95
[1360] DSI_CMD+0080 : 0x4712c353 0xc6800d11 0x84554fb7 0xebd45444
[1360] DSI_CMD+0090 : 0x4b067445 0x84751146 0x733f15bd 0x19936d6f
[1360] DSI_CMD+00a0 : 0xb3530de1 0x0d17e508 0x4a246d30 0x6551df1c
[1380] DSI_CMD+00b0 : 0x42686bd1 0xf9287cf8 0xd37f0991 0xdacd707a
[1380] DSI_CMD+00c0 : 0x9cdb8955 0x1f82e1ce 0x20f0f876 0xbb17fd0e
[1380] DSI_CMD+00d0 : 0x533b98ba 0x04535bdc 0xe79a65ff 0x3421dbb1
[1380] DSI_CMD+00e0 : 0xefb40d55 0x1cdde64f 0x3f575591 0x521bd001
[1380] DSI_CMD+00f0 : 0x232d15d5 0x45572548 0xa4c47f4d 0x14749f66
[1380] DSI_CMD+0100 : 0x735f78cf 0x44fb44e5 0x57ec5513 0xf96a4dd8
[1380] DSI_CMD+0110 : 0xb8411748 0x79754808 0xae674c55 0x77d36f37
[1380] DSI_CMD+0120 : 0x91711452 0x559d6c32 0x96cc3dad 0x039aa1d2
[1380] DSI_CMD+0130 : 0x557d7205 0x8edd7656 0x278375e5 0xcd5fd157
[1380] DSI_CMD+0140 : 0x575cd67d 0xdc3c4919 0xe1d93340 0x9169999b
[1380] DSI_CMD+0150 : 0x419ed5d8 0xf26fcd50 0x73f50cc1 0xa8096178
[1380] DSI_CMD+0160 : 0xa6735b55 0x42d93d56 0x71d674db 0xbcd18bfd
[1380] DSI_CMD+0170 : 0xc7f817c8 0x5d75c925 0xf6b59901 0xd33735b9
[1400] DSI_CMD+0180 : 0xb55dd961 0x371417e8 0xd9596103 0x9e6bf1f1
[1400] DSI_CMD+0190 : 0x14d91fd5 0x08c30938 0x55478378 0x4eb22503
[1400] DSI_CMD+01a0 : 0xdd572651 0x179d3d1f 0xfbd09750 0xdfbf9407
[1400] DSI_CMD+01b0 : 0x92d1e931 0x9ad8cf8b 0x94e0e442 0x9a79b5d5
[1400] DSI_CMD+01c0 : 0x45a4f911 0xa5a53535 0x6031c351 0x57967a81
[1400] DSI_CMD+01d0 : 0x1b172371 0x142c5772 0x08097093 0xb198451c
[1400] DSI_CMD+01e0 : 0x5dd3c66e 0x43966fd5 0x50047605 0xf3477857
[1400] DSI_CMD+01f0 : 0x4cb1d7e7 0xf7312d59 0xa7f44f01 0xf2104578
[1400] DSI_PHY+0000 : 0x00000403 0x00000821 0x00000401 0x00000101
[1400] DSI_PHY+0010 : 0x00000101 0x00000101 0x00000000 0x00000000
[1400] DSI_PHY+0020 : 0x00000000 0x00000000 0x00000000 0x00000000
[1400] DSI_PHY+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[1400] DSI_PHY+0040 : 0x00000082 0x88492483 0x00000000 0x00000000
[1420] DSI_PHY+0050 : 0x00000001 0x01b10007 0x26762762 0x048b048b
[1420] DSI_PHY+0060 : 0x00000001 0x00000020 0x00000101 0x00000000
[1420] DSI_PHY+0070 : 0x00000000 0x00000000 0x00000000 0x00043210
[1420] DSI_PHY+0080 : 0x00000000 0x00000000 0x00000000 0x00000000
[1420] DSI_PHY+0090 : 0x00000000 0x00000000 0x00000000 0x00000000
[1420] [DISP]func|DSI_dcs_read_lcm_reg_v2
[1420] DISP/ Start polling DSI read ready!!!
[1460] DISP/ Polling DSI read ready timeout!!!
[1460] DSI0 state:Waiting RX-read data
[1460] DSI Mode: lane num: transfer count: status: [1460] ---------- Start dump DSI0 registers ----------
[1460] DSI+0000 : 0x00000001 0x00000000 0x00000000 0x80000000
[1460] DSI+0010 : 0x00000000 0x00000000 0x0000007c 0x00030870
[1460] DSI+0020 : 0x00000008 0x00000010 0x00000010 0x00000500
[1460] DSI+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[1460] DSI+0040 : 0x00000000 0x00000000 0x00000000 0x00000000
[1480] DSI+0050 : 0x0000001c 0x00000104 0x000000e4 0x00000000
[1480] DSI+0060 : 0x00000001 0x00010000 0x00000000 0x00000000
[1480] DSI+0070 : 0x00000000 0x00000000 0x00000000 0x00000000
[1480] DSI+0080 : 0x00000000 0x00000000 0x00000020 0x00000000
[1480] DSI+0090 : 0x0000003c 0x00000000 0x00000000 0x00000000
[1480] DSI+00a0 : 0x00060080 0x00002000 0x00000000 0x00000000
[1480] DSI+00b0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1480] DSI+00c0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1480] DSI+00d0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1480] DSI+00e0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1480] DSI+00f0 : 0x00000000 0x00000000 0x00000000 0x00000000
[1480] DSI+0100 : 0x00000055 0x00000000 0x00000000 0x000000b8
[1480] DSI+0110 : 0x78090404 0x08140610 0x06170100 0x00080e03
[1480] DSI+0120 : 0x00000000 0x00000000 0x00000000 0x00000000
[1500] DSI+0130 : 0x00000021 0x00000000 0x00000000 0x00000000
[1500] DSI+0140 : 0x00000000 0x00000000 0x00010001 0x01010100
[1500] DSI+0150 : 0x01080001 0x01010101 0x00000101 0x10000000
[1500] DSI+0160 : 0x00010200 0x00000001 0x00000000 0x00000000
[1500] DSI+0170 : 0x00000000 0xfff00000 0x00000000 0x00200000
[1500] DSI_CMD+0000 : 0x00020604 0x8198ffff 0x00000104 0x65c96dc6
[1500] DSI_CMD+0010 : 0x1fb52006 0x60160a3e 0xd9e50d77 0x5c42a90f
[1500] DSI_CMD+0020 : 0x787b9491 0x28f55582 0x10657df7 0xe3f39022
[1500] DSI_CMD+0030 : 0x2838feb6 0x9cb8d0d0 0x69527205 0xf6b5d582
[1500] DSI_CMD+0040 : 0xa2ee65c0 0xd474745e 0x11cfefd0 0xd1d41e17
[1500] DSI_CMD+0050 : 0x705d471d 0x57491712 0x5fc7505e 0xd27597c7
[1500] DSI_CMD+0060 : 0x5af0125b 0x5f53104f 0xd51b97fb 0x8e2651ad
[1500] DSI_CMD+0070 : 0xd736f643 0x8124585e 0x1f52c105 0xdd949d95
[1510] DSI_CMD+0080 : 0x4712c353 0xc6800d11 0x84554fb7 0xebd45444
[1520] DSI_CMD+0090 : 0x4b067445 0x84751146 0x733f15bd 0x19936d6f
[1520] DSI_CMD+00a0 : 0xb3530de1 0x0d17e508 0x4a246d30 0x6551df1c
[1520] DSI_CMD+00b0 : 0x42686bd1 0xf9287cf8 0xd37f0991 0xdacd707a
[1520] DSI_CMD+00c0 : 0x9cdb8955 0x1f82e1ce 0x20f0f876 0xbb17fd0e
[1520] DSI_CMD+00d0 : 0x533b98ba 0x04535bdc 0xe79a65ff 0x3421dbb1
[1520] DSI_CMD+00e0 : 0xefb40d55 0x1cdde64f 0x3f575591 0x521bd001
[1520] DSI_CMD+00f0 : 0x232d15d5 0x45572548 0xa4c47f4d 0x14749f66
[1520] DSI_CMD+0100 : 0x735f78cf 0x44fb44e5 0x57ec5513 0xf96a4dd8
[1520] DSI_CMD+0110 : 0xb8411748 0x79754808 0xae674c55 0x77d36f37
[1520] DSI_CMD+0120 : 0x91711452 0x559d6c32 0x96cc3dad 0x039aa1d2
[1520] DSI_CMD+0130 : 0x557d7205 0x8edd7656 0x278375e5 0xcd5fd157
[1520] DSI_CMD+0140 : 0x575cd67d 0xdc3c4919 0xe1d93340 0x9169999b
[1520] DSI_CMD+0150 : 0x419ed5d8 0xf26fcd50 0x73f50cc1 0xa8096178
[1540] DSI_CMD+0160 : 0xa6735b55 0x42d93d56 0x71d674db 0xbcd18bfd
[1540] DSI_CMD+0170 : 0xc7f817c8 0x5d75c925 0xf6b59901 0xd33735b9
[1540] DSI_CMD+0180 : 0xb55dd961 0x371417e8 0xd9596103 0x9e6bf1f1
[1540] DSI_CMD+0190 : 0x14d91fd5 0x08c30938 0x55478378 0x4eb22503
[1540] DSI_CMD+01a0 : 0xdd572651 0x179d3d1f 0xfbd09750 0xdfbf9407
[1540] DSI_CMD+01b0 : 0x92d1e931 0x9ad8cf8b 0x94e0e442 0x9a79b5d5
[1540] DSI_CMD+01c0 : 0x45a4f911 0xa5a53535 0x6031c351 0x57967a81
[1540] DSI_CMD+01d0 : 0x1b172371 0x142c5772 0x08097093 0xb198451c
[1540] DSI_CMD+01e0 : 0x5dd3c66e 0x43966fd5 0x50047605 0xf3477857
[1540] DSI_CMD+01f0 : 0x4cb1d7e7 0xf7312d59 0xa7f44f01 0xf2104578
[1540] DSI_PHY+0000 : 0x00000403 0x00000821 0x00000401 0x00000101
[1540] DSI_PHY+0010 : 0x00000101 0x00000101 0x00000000 0x00000000
[1540] DSI_PHY+0020 : 0x00000000 0x00000000 0x00000000 0x00000000
[1560] DSI_PHY+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[1560] DSI_PHY+0040 : 0x00000082 0x88492483 0x00000000 0x00000000
[1560] DSI_PHY+0050 : 0x00000001 0x01b10007 0x26762762 0x048b048b
[1560] DSI_PHY+0060 : 0x00000001 0x00000020 0x00000101 0x00000000
[1560] DSI_PHY+0070 : 0x00000000 0x00000000 0x00000000 0x00043210
[1560] DSI_PHY+0080 : 0x00000000 0x00000000 0x00000000 0x00000000
[1560] DSI_PHY+0090 : 0x00000000 0x00000000 0x00000000 0x00000000
[LK]------ili9881 read id = 0x0, 0x0, 0x0---------
[1560] [DISP]func|_display_interface_path_deinit
[1560] [LK_DDP/ddp_manager]path deinit on scenario display_interface
[1560] [LK_DDP/ddp_path]mutex 0 clear
[1560] [LK_DDP/ddp_path]path disconnect on scenario display_interface
[1560] [LK_DDP/ddp_path]disconnect_path: ovl0 to dsi0
[1560] [LK_DDP/ddp_path]disconnect mout ovl0 to color0
[1580] [LK_DDP/ddp_path]disconnect mout dither to rdma0
[1580] [LK_DDP/ddp_manager]scenario display_interface deinit module ovl0
[1580] [LK_DDP/OVL]OVL0DeInit close CG
[1580] [LK_DDP/INFO]disable ovl0 clk, CG0 0xfffcb7fc, CG1 0xfffffff0,dummy CON = 0xfffcb7fc
[1580] [LK_DDP/ddp_manager]scenario display_interface deinit module color0
[1580] [LK_DDP/INFO]disable color0 clk, CG0 0xfffcf7fc, CG1 0xfffffff0,dummy CON = 0xfffcf7fc
[1580] [LK_DDP/ddp_manager]scenario display_interface deinit module aal
[1580] [LK_DDP/INFO]disable aal clk, CG0 0xfffdf7fc, CG1 0xfffffff0,dummy CON = 0xfffdf7fc
[1580] [LK_DDP/ddp_manager]scenario display_interface deinit module gamma
[1580] [LK_DDP/INFO]disable gamma clk, CG0 0xfffff7fc, CG1 0xfffffff0,dummy CON = 0xfffff7fc
[1580] [LK_DDP/ddp_manager]scenario display_interface deinit module rdma0
[1580] [LK_DDP/RDMA]RDMA0Deinit
[1580] [LK_DDP/INFO]disable rdma0 clk, CG0 0xfffffffc, CG1 0xfffffff0,dummy CON = 0xfffffffc
[1600] [LK_DDP/ddp_manager]scenario display_interface deinit module dsi0
[1600] [DISPCHECK]dsi0 init finished
[1600] [LK_DDP/INFO]disable dsi0 clk, CG0 0xfffffffc, CG1 0xfffffffc,dummy CON = 0xfffffffc
[1600] [DISP][mipitx/reg]0x14018084=0x00000001
[1600] [DISP][mipitx/reg]0x14018084=0x00000003
[1600] [DISP][mipitx/reg]0x14018084=0x00000013
[1600] [DISP][mipitx/reg]0x14018084=0x00000033
[1600] [DISP][mipitx/reg]0x14018084=0x00000033
[1600] [DISP][mipitx/reg]0x14018084=0x00000033
[1600] [DISP][mipitx/reg]0x14018084=0x00000133
[1600] [DISP][mipitx/reg]0x14018084=0x00000333
[1600] [DISP][mipitx/reg]0x14018084=0x00010333
[1600] [DISP][mipitx/reg]0x14018084=0x00020333
[1600] [DISP][mipitx/reg]0x14018084=0x00100333
[1600] [DISP][mipitx/reg]0x14018084=0x00200333
[1600] [DISP][mipitx/reg]0x14018080=0x00000001
[1600] [DISP][mipitx/reg]0x14018050=0x00000000
[1620] [DISP][mipitx/reg]0x14018064=0x00000020
[1620] [DISP][mipitx/reg]0x14018040=0x00000882
[1620] [DISP][mipitx/reg]0x14018004=0x00000820
[1620] [DISP][mipitx/reg]0x14018008=0x00000400
[1620] [DISP][mipitx/reg]0x1401800c=0x00000100
[1620] [DISP][mipitx/reg]0x14018010=0x00000100
[1620] [DISP][mipitx/reg]0x14018014=0x00000100
[1620] [DISP][mipitx/reg]0x14018068=0x00000103
[1620] [DISP][mipitx/reg]0x14018068=0x00000102
[1620] [DISP][mipitx/reg]0x14018040=0x00000880
[1620] [DISP][mipitx/reg]0x14018000=0x00000401
[1620] [DISP][mipitx/reg]0x14018000=0x00000400
[1620] [DISP][mipitx/reg]0x14018044=0x88492481
[1620] [DISP][mipitx/reg]0x14018044=0x88492480
[1620] [DISP][mipitx/reg]0x14018050=0x00000000
[1620] [DISP][mipitx/reg]0x14018050=0x00000000
[1620] [DISP][mipitx/reg]0x14018050=0x00000000
[1630] [DISP][mipitx/reg]0x14018050=0x00000000
[1640] [DISP][mipitx/reg]0x14018054=0x00000000
[1640] [DISP][mipitx/reg]0x14018058=0x50000000
[1640] [DISP][mipitx/reg]0x14018080=0x00000000
[1640] [LK_DDP/ddp_manager]destroy path handle 0x41e69f40 on scenario display_interface
[1640] [LK_DDP/ddp_manager]release mutex 0 , left mutex 0x1f!
[1640] [LK_DDP/ddp_path]path disconnect on scenario display_interface
[1640] [LK_DDP/ddp_path]disconnect_path: ovl0 to dsi0
[1640] [LK_DDP/ddp_path]disconnect mout ovl0 to color0
[1640] [LK_DDP/ddp_path]disconnect mout dither to rdma0
[1640] [DISP]we will check lcm: jd9522_hd720_dsi_vdo_qc
[1640] [DISP]func|_display_interface_path_init
[1640] [LK_DDP/ddp_manager]scenario display_interface acquire mutex 0 , left mutex 0x1e!
[1640] [LK_DDP/ddp_manager]assign default irqs table index 0
[1660] [LK_DDP/ddp_manager]create handle 0x41e69f40 on scenario display_interface
[1660] [LK_DDP/ddp_manager] scenario display_interface include module ovl0
[1660] [LK_DDP/ddp_manager] scenario display_interface include module color0
[1660] [LK_DDP/ddp_manager] scenario display_interface include module ccorr
[1660] [LK_DDP/ddp_manager] scenario display_interface include module aal
[1660] [LK_DDP/ddp_manager] scenario display_interface include module gamma
[1660] [LK_DDP/ddp_manager] scenario display_interface include module dither
[1660] [LK_DDP/ddp_manager] scenario display_interface include module rdma0
[1660] [LK_DDP/ddp_manager] scenario display_interface include module pwm0
[1660] [LK_DDP/ddp_manager] scenario display_interface include module dsi0
[1660] [DISPCHECK]dpmgr create path SUCCESS(0x41e69f40)
[1660] [LK_DDP/ddp_manager]set dst module on scenario display_interface, module dsi0
[1670] [LK_DDP/ddp_path]ddp_set_dst_module, scenario=display_interface, dst_module=dsi0
[1680] [LK_DDP/ddp_path]dsi0 is already on path
[1680] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[1680] [LK_DDP/ddp_manager]path set lcm drv handle 0x41e69f40
[1680] [LK_DDP/ddp_manager]dsi0 set lcm utils
[1680] [LK_DDP/ddp_manager]path init on scenario display_interface
[1680] [LK_DDP/ddp_path]ddp path m4u off
[1680] [LK_DDP/ddp_path]ddp path top clock on
[1680] [LK_DDP/INFO]enable smi clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[1680] [LK_DDP/INFO]enable mutex clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[1680] [LK_DDP/ddp_path]ddp CG:fffffffc
[1680] [LK_DDP/ddp_path]mutex sof: dsi0 dst module dsi0 :vido_mode
[1680] [LK_DDP/ddp_path]module ovl0 added to mutex 0
[1680] [LK_DDP/ddp_path]module color0 added to mutex 0
[1680] [LK_DDP/ddp_path]module ccorr added to mutex 0
[1690] [LK_DDP/ddp_path]module aal added to mutex 0
[1700] [LK_DDP/ddp_path]module gamma added to mutex 0
[1700] [LK_DDP/ddp_path]module dither added to mutex 0
[1700] [LK_DDP/ddp_path]module rdma0 added to mutex 0
[1700] [LK_DDP/ddp_path]module pwm0 added to mutex 0
[1700] [LK_DDP/ddp_path]mutex 0 value=0x2f940, sof=dsi0
[1700] [LK_DDP/ddp_path]path connect on scenario display_interface
[1700] [LK_DDP/ddp_path]connect_path: ovl0 to dsi0
[1700] [LK_DDP/ddp_path]connect mout ovl0 to color0 value 0x1
[1700] [LK_DDP/ddp_path]connect mout dither to rdma0 value 0x1
[1700] [LK_DDP/ddp_path]connect out_s rdma0 to dsi0 , bits=0x2
[1700] [LK_DDP/ddp_path]connect in_s ovl0 to color0 , bits=0x1
[1700] [LK_DDP/ddp_path]connect in_s rdma0 to dsi0 , bits=0x1
[1700] [LK_DDP/ddp_manager]scenario display_interface init module ovl0
[1700] [LK_DDP/INFO]enable ovl0 clk, CG0 0xfffffbfc, CG1 0xfffffffc, dummy CON = 0xfffffbfc
[1720] [LK_DDP/OVL]OVL0Init open CG 0xfffffbfc
[1720] [LK_DDP/ddp_manager]scenario display_interface init module color0
[1720] [LK_DDP/INFO]enable color0 clk, CG0 0xffffbbfc, CG1 0xfffffffc, dummy CON = 0xffffbbfc
[1720] [LK_DDP/ddp_manager]scenario display_interface init module aal
[1720] [LK_DDP/INFO]enable aal clk, CG0 0xfffebbfc, CG1 0xfffffffc, dummy CON = 0xfffebbfc
[1720] [LK_DDP/ddp_manager]scenario display_interface init module gamma
[1720] [LK_DDP/INFO]enable gamma clk, CG0 0xfffcbbfc, CG1 0xfffffffc, dummy CON = 0xfffcbbfc
[1720] [LK_DDP/ddp_manager]scenario display_interface init module rdma0
[1720] [LK_DDP/INFO]enable rdma0 clk, CG0 0xfffcb3fc, CG1 0xfffffffc, dummy CON = 0xfffcb3fc
[1720] [LK_DDP/RDMA]RDMA0Init CG 0xfffcb3fc
[1720] [LK_DDP/ddp_manager]scenario display_interface init module dsi0
[1720] [DISP]func|ddp_dsi_init
[1720] [LK_DDP/INFO]enable dsi0 clk, CG0 0xfffcb3fc, CG1 0xfffffff0, dummy CON = 0xfffcb3fc
[1740] [DISPCHECK]dsi0 init finished
[1740] [LK_DDP/ddp_manager]path config ovl 0, rdma 0, wdma 0, dst 1 on handle 0x41e69f40 scenario display_interface
[1740] [LK_DDP/ddp_manager]scenario display_interface config module ovl0
[1740] [LK_DDP/ddp_manager]scenario display_interface config module color0
[1740] [LK_DDP/ddp_manager]scenario display_interface config module aal
[1740] [LK_DDP/ddp_manager]scenario display_interface config module gamma
[1740] [LK_DDP/ddp_manager]scenario display_interface config module dither
[1740] [LK_DDP/DITHER]error:[DITHER] invalid dither bpp = 0
[1740] [LK_DDP/ddp_manager]scenario display_interface config module rdma0
[1740] [LK_DDP/RDMA]FIFO_VALID_Size = 0x020 = 32
[1740] [LK_DDP/RDMA]ultra_low_level = 0x06b = 107
[1740] [LK_DDP/RDMA]pre_ultra_low_level = 0x05f = 95
[1740] [LK_DDP/RDMA]pre_ultra_high_level = 0x06b = 107
[1760] [LK_DDP/RDMA]ultra_high_ofs = 0x001 = 1
[1760] [LK_DDP/RDMA]pre_ultra_low_ofs = 0x0a0 = 160
[1760] [LK_DDP/RDMA]pre_ultra_high_ofs = 0x001 = 1
[1760] [LK_DDP/ddp_manager]scenario display_interface config module dsi0
[1760] [DISP]func|ddp_dsi_config
[1760] [DISPCHECK][DDPDSI] DSI Mode: BURST_VDO_MODE
[1760] [DISPCHECK][DDPDSI] LANE_NUM: 2,data_format: 0,vertical_sync_active: 0
[1760] [DISPCHECK][DDPDSI] vact: 2, vbp: 4, vfp: 8, vact_line: 1280, hact: 20, hbp: 20, hfp: 80, hblank: 0
[1760] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[1760] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 400, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[1760] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[1760] [DISP]func|DSI_PHY_clk_setting
[1780] [DISP][mipitx/reg]0x14018044=0x88492481
[1780] [DISP][mipitx/reg]0x14018044=0x88492483
[1780] [DISP][mipitx/reg]0x14018040=0x00000882
[1780] [DISP][mipitx/reg]0x14018000=0x00000402
[1780] [DISP][mipitx/reg]0x14018000=0x00000403
[1780] [DISP][mipitx/reg]0x14018068=0x00000003
[1780] [DISP][mipitx/reg]0x14018068=0x00000101
[1780] [DISP][mipitx/reg]0x14018050=0x00000000
[1780] [DISP][mipitx/reg]0x14018050=0x00000000
[1780] [DISP][mipitx/reg]0x14018050=0x00000000
[1780] [DISP][mipitx/reg]0x14018054=0x00000001
[1780] [DISP][mipitx/reg]0x14018058=0x3d000000
[1780] [DISP][mipitx/reg]0x14018058=0x3d890000
[1780] [DISP][mipitx/reg]0x14018058=0x3d89d800
[1780] [DISP][mipitx/reg]0x14018058=0x3d89d89d
[1780] [DISP][mipitx/reg]0x14018054=0x00000003
[1780] [DISP][mipitx/reg]0x14018054=0x01b10003
[1780] [DISP][mipitx/reg]0x1401805c=0x0745048b
[1780] [DISP][mipitx/reg]0x1401805c=0x07450745
[1790] [DISP][dsi_drv.c] PLL config:data_rate=800,txdiv=1,pcw=1032444061,delta1=5,pdelta1=0x745
[1800] [DISP][mipitx/reg]0x14018054=0x01b10007
[1800] [DISP][mipitx/reg]0x14018004=0x00000821
[1800] [DISP][mipitx/reg]0x14018008=0x00000401
[1800] [DISP][mipitx/reg]0x1401800c=0x00000101
[1800] [DISP][mipitx/reg]0x14018050=0x00000001
[1800] [DISP][mipitx/reg]0x14018060=0x00000000
[1800] [DISP][mipitx/reg]0x14018060=0x00000001
[1800] [DISP][mipitx/reg]0x14018040=0x00000082
[1800] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 11(ns), Unit Interval = 2(ns). , lane# = 2
[1800] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 8, HS_ZERO = 14, HS_PRPR = 6, LPX = 7, TA_GET = 35, TA_SURE = 10, TA_GO = 28, CLK_TRAIL = 9, CLK_ZERO = 36, CLK_HS_PRPR = 5
[1800] DSI_PHY_TIMCONFIG, 0x080e0607,0x0e230a1c,0x09240100,0x000e1205
[2040] [DISP]func|DSI_set_cmdq
[2040] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[2040] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0000 : 0x00043902
[2040] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0004 : 0xb72295df
[2060] [DISP]func|DSI_set_cmdq
[2060] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[2080] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0000 : 0x00043700
[2100] [DISP]func|DSI_dcs_read_lcm_reg_v2
[2100] DISP/ Start polling DSI read ready!!!
[2140] DISP/ Polling DSI read ready timeout!!!
[2140] DSI0 state:Waiting RX-read data
[2140] DSI Mode: lane num: transfer count: status: [2140] ---------- Start dump DSI0 registers ----------
[2140] DSI+0000 : 0x00000001 0x00000000 0x00000000 0x80000000
[2140] DSI+0010 : 0x00000000 0x00000000 0x0000004c 0x00030870
[2140] DSI+0020 : 0x00000002 0x00000004 0x00000008 0x00000500
[2140] DSI+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[2140] DSI+0040 : 0x00000000 0x00000000 0x00000000 0x00000000
[2140] DSI+0050 : 0x00000038 0x00000070 0x000000e4 0x00000000
[2140] DSI+0060 : 0x00000001 0x00010000 0x00000000 0x00000000
[2140] DSI+0070 : 0x00000000 0x00000000 0x00000000 0x00000000
[2140] DSI+0080 : 0x00000000 0x00000000 0x00000020 0x00000000
[2160] DSI+0090 : 0x0000003c 0x00000000 0x00000000 0x00000000
[2160] DSI+00a0 : 0x00060080 0x00002000 0x00000000 0x00000000
[2160] DSI+00b0 : 0x00000000 0x00000000 0x00000000 0x00000000
[2160] DSI+00c0 : 0x00000000 0x00000000 0x00000000 0x00000000
[2160] DSI+00d0 : 0x00000000 0x00000000 0x00000000 0x00000000
[2160] DSI+00e0 : 0x00000000 0x00000000 0x00000000 0x00000000
[2160] DSI+00f0 : 0x00000000 0x00000000 0x00000000 0x00000000
[2160] DSI+0100 : 0x00000055 0x00000000 0x00000000 0x000000b8
[2160] DSI+0110 : 0x080e0607 0x0e230a1c 0x09240100 0x000e1205
[2160] DSI+0120 : 0x00000000 0x00000000 0x00000000 0x00000000
[2160] DSI+0130 : 0x00000021 0x00000000 0x00000000 0x00000000
[2160] DSI+0140 : 0x00000000 0x00000000 0x00010001 0x01010100
[2160] DSI+0150 : 0x01080001 0x01010101 0x00000101 0x10000000
[2160] DSI+0160 : 0x00010200 0x00000001 0x00000000 0x00000000
[2180] DSI+0170 : 0x00000000 0xfff00000 0x00000000 0x00200000
[2180] DSI_CMD+0000 : 0x00040604 0xb72295df 0x00000104 0x65c96dc6
[2180] DSI_CMD+0010 : 0x1fb52006 0x60160a3e 0xd9e50d77 0x5c42a90f
[2180] DSI_CMD+0020 : 0x787b9491 0x28f55582 0x10657df7 0xe3f39022
[2180] DSI_CMD+0030 : 0x2838feb6 0x9cb8d0d0 0x69527205 0xf6b5d582
[2180] DSI_CMD+0040 : 0xa2ee65c0 0xd474745e 0x11cfefd0 0xd1d41e17
[2180] DSI_CMD+0050 : 0x705d471d 0x57491712 0x5fc7505e 0xd27597c7
[2180] DSI_CMD+0060 : 0x5af0125b 0x5f53104f 0xd51b97fb 0x8e2651ad
[2180] DSI_CMD+0070 : 0xd736f643 0x8124585e 0x1f52c105 0xdd949d95
[2180] DSI_CMD+0080 : 0x4712c353 0xc6800d11 0x84554fb7 0xebd45444
[2180] DSI_CMD+0090 : 0x4b067445 0x84751146 0x733f15bd 0x19936d6f
[2180] DSI_CMD+00a0 : 0xb3530de1 0x0d17e508 0x4a246d30 0x6551df1c
[2180] DSI_CMD+00b0 : 0x42686bd1 0xf9287cf8 0xd37f0991 0xdacd707a
[2190] DSI_CMD+00c0 : 0x9cdb8955 0x1f82e1ce 0x20f0f876 0xbb17fd0e
[2200] DSI_CMD+00d0 : 0x533b98ba 0x04535bdc 0xe79a65ff 0x3421dbb1
[2200] DSI_CMD+00e0 : 0xefb40d55 0x1cdde64f 0x3f575591 0x521bd001
[2200] DSI_CMD+00f0 : 0x232d15d5 0x45572548 0xa4c47f4d 0x14749f66
[2200] DSI_CMD+0100 : 0x735f78cf 0x44fb44e5 0x57ec5513 0xf96a4dd8
[2200] DSI_CMD+0110 : 0xb8411748 0x79754808 0xae674c55 0x77d36f37
[2200] DSI_CMD+0120 : 0x91711452 0x559d6c32 0x96cc3dad 0x039aa1d2
[2200] DSI_CMD+0130 : 0x557d7205 0x8edd7656 0x278375e5 0xcd5fd157
[2200] DSI_CMD+0140 : 0x575cd67d 0xdc3c4919 0xe1d93340 0x9169999b
[2200] DSI_CMD+0150 : 0x419ed5d8 0xf26fcd50 0x73f50cc1 0xa8096178
[2200] DSI_CMD+0160 : 0xa6735b55 0x42d93d56 0x71d674db 0xbcd18bfd
[2200] DSI_CMD+0170 : 0xc7f817c8 0x5d75c925 0xf6b59901 0xd33735b9
[2200] DSI_CMD+0180 : 0xb55dd961 0x371417e8 0xd9596103 0x9e6bf1f1
[2200] DSI_CMD+0190 : 0x14d91fd5 0x08c30938 0x55478378 0x4eb22503
[2220] DSI_CMD+01a0 : 0xdd572651 0x179d3d1f 0xfbd09750 0xdfbf9407
[2220] DSI_CMD+01b0 : 0x92d1e931 0x9ad8cf8b 0x94e0e442 0x9a79b5d5
[2220] DSI_CMD+01c0 : 0x45a4f911 0xa5a53535 0x6031c351 0x57967a81
[2220] DSI_CMD+01d0 : 0x1b172371 0x142c5772 0x08097093 0xb198451c
[2220] DSI_CMD+01e0 : 0x5dd3c66e 0x43966fd5 0x50047605 0xf3477857
[2220] DSI_CMD+01f0 : 0x4cb1d7e7 0xf7312d59 0xa7f44f01 0xf2104578
[2220] DSI_PHY+0000 : 0x00000403 0x00000821 0x00000401 0x00000101
[2220] DSI_PHY+0010 : 0x00000100 0x00000100 0x00000000 0x00000000
[2220] DSI_PHY+0020 : 0x00000000 0x00000000 0x00000000 0x00000000
[2220] DSI_PHY+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[2220] DSI_PHY+0040 : 0x00000082 0x88492483 0x00000000 0x00000000
[2220] DSI_PHY+0050 : 0x00000001 0x01b10007 0x3d89d89d 0x07450745
[2220] DSI_PHY+0060 : 0x00000001 0x00000020 0x00000101 0x00000000
[2240] DSI_PHY+0070 : 0x00000000 0x00000000 0x00000000 0x00043210
[2240] DSI_PHY+0080 : 0x00000000 0x00000333 0x00000000 0x00000000
[2240] DSI_PHY+0090 : 0x00000000 0x00000000 0x00000000 0x00000000
[u-boot] jd9522 , device_id = 0x0
[2240] [DISP]func|_display_interface_path_deinit
[2240] [LK_DDP/ddp_manager]path deinit on scenario display_interface
[2240] [LK_DDP/ddp_path]mutex 0 clear
[2240] [LK_DDP/ddp_path]path disconnect on scenario display_interface
[2240] [LK_DDP/ddp_path]disconnect_path: ovl0 to dsi0
[2240] [LK_DDP/ddp_path]disconnect mout ovl0 to color0
[2240] [LK_DDP/ddp_path]disconnect mout dither to rdma0
[2240] [LK_DDP/ddp_manager]scenario display_interface deinit module ovl0
[2240] [LK_DDP/OVL]OVL0DeInit close CG
[2240] [LK_DDP/INFO]disable ovl0 clk, CG0 0xfffcb7fc, CG1 0xfffffff0,dummy CON = 0xfffcb7fc
[2240] [LK_DDP/ddp_manager]scenario display_interface deinit module color0
[2260] [LK_DDP/INFO]disable color0 clk, CG0 0xfffcf7fc, CG1 0xfffffff0,dummy CON = 0xfffcf7fc
[2260] [LK_DDP/ddp_manager]scenario display_interface deinit module aal
[2260] [LK_DDP/INFO]disable aal clk, CG0 0xfffdf7fc, CG1 0xfffffff0,dummy CON = 0xfffdf7fc
[2260] [LK_DDP/ddp_manager]scenario display_interface deinit module gamma
[2260] [LK_DDP/INFO]disable gamma clk, CG0 0xfffff7fc, CG1 0xfffffff0,dummy CON = 0xfffff7fc
[2260] [LK_DDP/ddp_manager]scenario display_interface deinit module rdma0
[2260] [LK_DDP/RDMA]RDMA0Deinit
[2260] [LK_DDP/INFO]disable rdma0 clk, CG0 0xfffffffc, CG1 0xfffffff0,dummy CON = 0xfffffffc
[2260] [LK_DDP/ddp_manager]scenario display_interface deinit module dsi0
[2260] [DISPCHECK]dsi0 init finished
[2260] [LK_DDP/INFO]disable dsi0 clk, CG0 0xfffffffc, CG1 0xfffffffc,dummy CON = 0xfffffffc
[2260] [DISP][mipitx/reg]0x14018084=0x00000333
[2280] [DISP][mipitx/reg]0x14018084=0x00000333
[2280] [DISP][mipitx/reg]0x14018084=0x00000333
[2280] [DISP][mipitx/reg]0x14018084=0x00000333
[2280] [DISP][mipitx/reg]0x14018084=0x00000333
[2280] [DISP][mipitx/reg]0x14018084=0x00000333
[2280] [DISP][mipitx/reg]0x14018084=0x00000333
[2280] [DISP][mipitx/reg]0x14018084=0x00000333
[2280] [DISP][mipitx/reg]0x14018084=0x00010333
[2280] [DISP][mipitx/reg]0x14018084=0x00020333
[2280] [DISP][mipitx/reg]0x14018084=0x00100333
[2280] [DISP][mipitx/reg]0x14018084=0x00200333
[2280] [DISP][mipitx/reg]0x14018080=0x00000001
[2280] [DISP][mipitx/reg]0x14018050=0x00000000
[2280] [DISP][mipitx/reg]0x14018064=0x00000020
[2280] [DISP][mipitx/reg]0x14018040=0x00000882
[2280] [DISP][mipitx/reg]0x14018004=0x00000820
[2280] [DISP][mipitx/reg]0x14018008=0x00000400
[2300] [DISP][mipitx/reg]0x1401800c=0x00000100
[2300] [DISP][mipitx/reg]0x14018010=0x00000100
[2300] [DISP][mipitx/reg]0x14018014=0x00000100
[2300] [DISP][mipitx/reg]0x14018068=0x00000103
[2300] [DISP][mipitx/reg]0x14018068=0x00000102
[2300] [DISP][mipitx/reg]0x14018040=0x00000880
[2300] [DISP][mipitx/reg]0x14018000=0x00000401
[2300] [DISP][mipitx/reg]0x14018000=0x00000400
[2300] [DISP][mipitx/reg]0x14018044=0x88492481
[2300] [DISP][mipitx/reg]0x14018044=0x88492480
[2300] [DISP][mipitx/reg]0x14018050=0x00000000
[2300] [DISP][mipitx/reg]0x14018050=0x00000000
[2300] [DISP][mipitx/reg]0x14018050=0x00000000
[2300] [DISP][mipitx/reg]0x14018050=0x00000000
[2300] [DISP][mipitx/reg]0x14018054=0x00000000
[2300] [DISP][mipitx/reg]0x14018058=0x50000000
[2300] [DISP][mipitx/reg]0x14018080=0x00000000
[2300] [LK_DDP/ddp_manager]destroy path handle 0x41e69f40 on scenario display_interface
[2320] [LK_DDP/ddp_manager]release mutex 0 , left mutex 0x1f!
[2320] [LK_DDP/ddp_path]path disconnect on scenario display_interface
[2320] [LK_DDP/ddp_path]disconnect_path: ovl0 to dsi0
[2320] [LK_DDP/ddp_path]disconnect mout ovl0 to color0
[2320] [LK_DDP/ddp_path]disconnect mout dither to rdma0
[2320] [DISP]ERROR:we have checked all lcm driver, but no lcm found
[2320] [DISP]func|_display_interface_path_init
[2320] [LK_DDP/ddp_manager]scenario display_interface acquire mutex 0 , left mutex 0x1e!
[2320] [LK_DDP/ddp_manager]assign default irqs table index 0
[2320] [LK_DDP/ddp_manager]create handle 0x41e69f40 on scenario display_interface
[2320] [LK_DDP/ddp_manager] scenario display_interface include module ovl0
[2320] [LK_DDP/ddp_manager] scenario display_interface include module color0
[2320] [LK_DDP/ddp_manager] scenario display_interface include module ccorr
[2340] [LK_DDP/ddp_manager] scenario display_interface include module aal
[2340] [LK_DDP/ddp_manager] scenario display_interface include module gamma
[2340] [LK_DDP/ddp_manager] scenario display_interface include module dither
[2340] [LK_DDP/ddp_manager] scenario display_interface include module rdma0
[2340] [LK_DDP/ddp_manager] scenario display_interface include module pwm0
[2340] [LK_DDP/ddp_manager] scenario display_interface include module dsi0
[2340] [DISPCHECK]dpmgr create path SUCCESS(0x41e69f40)
[2340] [LK_DDP/ddp_manager]set dst module on scenario display_interface, module dsi0
[2340] [LK_DDP/ddp_path]ddp_set_dst_module, scenario=display_interface, dst_module=dsi0
[2340] [LK_DDP/ddp_path]dsi0 is already on path
[2340] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[2340] [LK_DDP/ddp_manager]path set lcm drv handle 0x41e69f40
[2340] [LK_DDP/ddp_manager]dsi0 set lcm utils
[2360] [LK_DDP/ddp_manager]path init on scenario display_interface
[2360] [LK_DDP/ddp_path]ddp path m4u off
[2360] [LK_DDP/ddp_path]ddp path top clock on
[2360] [LK_DDP/INFO]enable smi clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[2360] [LK_DDP/INFO]enable mutex clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[2360] [LK_DDP/ddp_path]ddp CG:fffffffc
[2360] [LK_DDP/ddp_path]mutex sof: dsi0 dst module dsi0 :vido_mode
[2360] [LK_DDP/ddp_path]module ovl0 added to mutex 0
[2360] [LK_DDP/ddp_path]module color0 added to mutex 0
[2360] [LK_DDP/ddp_path]module ccorr added to mutex 0
[2360] [LK_DDP/ddp_path]module aal added to mutex 0
[2360] [LK_DDP/ddp_path]module gamma added to mutex 0
[2360] [LK_DDP/ddp_path]module dither added to mutex 0
[2360] [LK_DDP/ddp_path]module rdma0 added to mutex 0
[2360] [LK_DDP/ddp_path]module pwm0 added to mutex 0
[2370] [LK_DDP/ddp_path]mutex 0 value=0x2f940, sof=dsi0
[2380] [LK_DDP/ddp_path]path connect on scenario display_interface
[2380] [LK_DDP/ddp_path]connect_path: ovl0 to dsi0
[2380] [LK_DDP/ddp_path]connect mout ovl0 to color0 value 0x1
[2380] [LK_DDP/ddp_path]connect mout dither to rdma0 value 0x1
[2380] [LK_DDP/ddp_path]connect out_s rdma0 to dsi0 , bits=0x2
[2380] [LK_DDP/ddp_path]connect in_s ovl0 to color0 , bits=0x1
[2380] [LK_DDP/ddp_path]connect in_s rdma0 to dsi0 , bits=0x1
[2380] [LK_DDP/ddp_manager]scenario display_interface init module ovl0
[2380] [LK_DDP/INFO]enable ovl0 clk, CG0 0xfffffbfc, CG1 0xfffffffc, dummy CON = 0xfffffbfc
[2380] [LK_DDP/OVL]OVL0Init open CG 0xfffffbfc
[2380] [LK_DDP/ddp_manager]scenario display_interface init module color0
[2380] [LK_DDP/INFO]enable color0 clk, CG0 0xffffbbfc, CG1 0xfffffffc, dummy CON = 0xffffbbfc
[2380] [LK_DDP/ddp_manager]scenario display_interface init module aal
[2400] [LK_DDP/INFO]enable aal clk, CG0 0xfffebbfc, CG1 0xfffffffc, dummy CON = 0xfffebbfc
[2400] [LK_DDP/ddp_manager]scenario display_interface init module gamma
[2400] [LK_DDP/INFO]enable gamma clk, CG0 0xfffcbbfc, CG1 0xfffffffc, dummy CON = 0xfffcbbfc
[2400] [LK_DDP/ddp_manager]scenario display_interface init module rdma0
[2400] [LK_DDP/INFO]enable rdma0 clk, CG0 0xfffcb3fc, CG1 0xfffffffc, dummy CON = 0xfffcb3fc
[2400] [LK_DDP/RDMA]RDMA0Init CG 0xfffcb3fc
[2400] [LK_DDP/ddp_manager]scenario display_interface init module dsi0
[2400] [DISP]func|ddp_dsi_init
[2400] [LK_DDP/INFO]enable dsi0 clk, CG0 0xfffcb3fc, CG1 0xfffffff0, dummy CON = 0xfffcb3fc
[2400] [DISPCHECK]dsi0 init finished
[2400] [LK_DDP/ddp_manager]path config ovl 0, rdma 0, wdma 0, dst 1 on handle 0x41e69f40 scenario display_interface
[2400] [LK_DDP/ddp_manager]scenario display_interface config module ovl0
[2420] [LK_DDP/ddp_manager]scenario display_interface config module color0
[2420] [LK_DDP/ddp_manager]scenario display_interface config module aal
[2420] [LK_DDP/ddp_manager]scenario display_interface config module gamma
[2420] [LK_DDP/ddp_manager]scenario display_interface config module dither
[2420] [LK_DDP/DITHER]error:[DITHER] invalid dither bpp = 0
[2420] [LK_DDP/ddp_manager]scenario display_interface config module rdma0
[2420] [LK_DDP/RDMA]FIFO_VALID_Size = 0x020 = 32
[2420] [LK_DDP/RDMA]ultra_low_level = 0x06b = 107
[2420] [LK_DDP/RDMA]pre_ultra_low_level = 0x05f = 95
[2420] [LK_DDP/RDMA]pre_ultra_high_level = 0x06b = 107
[2420] [LK_DDP/RDMA]ultra_high_ofs = 0x001 = 1
[2420] [LK_DDP/RDMA]pre_ultra_low_ofs = 0x0a0 = 160
[2420] [LK_DDP/RDMA]pre_ultra_high_ofs = 0x001 = 1
[2420] [LK_DDP/ddp_manager]scenario display_interface config module dsi0
[2440] [DISP]func|ddp_dsi_config
[2440] [DISPCHECK][DDPDSI] DSI Mode: BURST_VDO_MODE
[2440] [DISPCHECK][DDPDSI] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[2440] [DISPCHECK][DDPDSI] vact: 8, vbp: 16, vfp: 16, vact_line: 1280, hact: 10, hbp: 80, hfp: 80, hblank: 0
[2440] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[2440] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 250, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[2440] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[2440] [DISP]func|DSI_PHY_clk_setting
[2440] [DISP][mipitx/reg]0x14018044=0x88492481
[2440] [DISP][mipitx/reg]0x14018044=0x88492483
[2440] [DISP][mipitx/reg]0x14018040=0x00000882
[2440] [DISP][mipitx/reg]0x14018000=0x00000402
[2440] [DISP][mipitx/reg]0x14018000=0x00000403
[2440] [DISP][mipitx/reg]0x14018068=0x00000003
[2460] [DISP][mipitx/reg]0x14018068=0x00000101
[2460] [DISP][mipitx/reg]0x14018050=0x00000000
[2460] [DISP][mipitx/reg]0x14018050=0x00000000
[2460] [DISP][mipitx/reg]0x14018050=0x00000000
[2460] [DISP][mipitx/reg]0x14018054=0x00000001
[2460] [DISP][mipitx/reg]0x14018058=0x26000000
[2460] [DISP][mipitx/reg]0x14018058=0x26760000
[2460] [DISP][mipitx/reg]0x14018058=0x26762700
[2460] [DISP][mipitx/reg]0x14018058=0x26762762
[2460] [DISP][mipitx/reg]0x14018054=0x00000003
[2460] [DISP][mipitx/reg]0x14018054=0x01b10003
[2460] [DISP][mipitx/reg]0x1401805c=0x048b0745
[2460] [DISP][mipitx/reg]0x1401805c=0x048b048b
[2460] [DISP][dsi_drv.c] PLL config:data_rate=500,txdiv=1,pcw=645277538,delta1=5,pdelta1=0x48b
[2460] [DISP][mipitx/reg]0x14018054=0x01b10007
[2460] [DISP][mipitx/reg]0x14018004=0x00000821
[2460] [DISP][mipitx/reg]0x14018008=0x00000401
[2460] [DISP][mipitx/reg]0x1401800c=0x00000101
[2480] [DISP][mipitx/reg]0x14018010=0x00000101
[2480] [DISP][mipitx/reg]0x14018014=0x00000101
[2480] [DISP][mipitx/reg]0x14018050=0x00000001
[2480] [DISP][mipitx/reg]0x14018060=0x00000000
[2480] [DISP][mipitx/reg]0x14018060=0x00000001
[2480] [DISP][mipitx/reg]0x14018040=0x00000082
[2480] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 17(ns), Unit Interval = 3(ns). , lane# = 4
[2480] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 120, HS_ZERO = 9, HS_PRPR = 4, LPX = 4, TA_GET = 20, TA_SURE = 6, TA_GO = 16, CLK_TRAIL = 6, CLK_ZERO = 23, CLK_HS_PRPR = 3
[2480] DSI_PHY_TIMCONFIG, 0x78090404,0x08140610,0x06170100,0x00080e03
[2480] [DISP]func|_display_interface_path_deinit
[2480] [LK_DDP/ddp_manager]path deinit on scenario display_interface
[2480] [LK_DDP/ddp_path]mutex 0 clear
[2480] [LK_DDP/ddp_path]path disconnect on scenario display_interface
[2480] [LK_DDP/ddp_path]disconnect_path: ovl0 to dsi0
[2500] [LK_DDP/ddp_path]disconnect mout ovl0 to color0
[2500] [LK_DDP/ddp_path]disconnect mout dither to rdma0
[2500] [LK_DDP/ddp_manager]scenario display_interface deinit module ovl0
[2500] [LK_DDP/OVL]OVL0DeInit close CG
[2500] [LK_DDP/INFO]disable ovl0 clk, CG0 0xfffcb7fc, CG1 0xfffffff0,dummy CON = 0xfffcb7fc
[2500] [LK_DDP/ddp_manager]scenario display_interface deinit module color0
[2500] [LK_DDP/INFO]disable color0 clk, CG0 0xfffcf7fc, CG1 0xfffffff0,dummy CON = 0xfffcf7fc
[2500] [LK_DDP/ddp_manager]scenario display_interface deinit module aal
[2500] [LK_DDP/INFO]disable aal clk, CG0 0xfffdf7fc, CG1 0xfffffff0,dummy CON = 0xfffdf7fc
[2500] [LK_DDP/ddp_manager]scenario display_interface deinit module gamma
[2500] [LK_DDP/INFO]disable gamma clk, CG0 0xfffff7fc, CG1 0xfffffff0,dummy CON = 0xfffff7fc
[2500] [LK_DDP/ddp_manager]scenario display_interface deinit module rdma0
[2520] [LK_DDP/RDMA]RDMA0Deinit
[2520] [LK_DDP/INFO]disable rdma0 clk, CG0 0xfffffffc, CG1 0xfffffff0,dummy CON = 0xfffffffc
[2520] [LK_DDP/ddp_manager]scenario display_interface deinit module dsi0
[2520] [DISPCHECK]dsi0 init finished
[2520] [LK_DDP/INFO]disable dsi0 clk, CG0 0xfffffffc, CG1 0xfffffffc,dummy CON = 0xfffffffc
[2520] [DISP][mipitx/reg]0x14018084=0x00000333
[2520] [DISP][mipitx/reg]0x14018084=0x00000333
[2520] [DISP][mipitx/reg]0x14018084=0x00000333
[2520] [DISP][mipitx/reg]0x14018084=0x00000333
[2520] [DISP][mipitx/reg]0x14018084=0x00000333
[2520] [DISP][mipitx/reg]0x14018084=0x00000333
[2520] [DISP][mipitx/reg]0x14018084=0x00000333
[2520] [DISP][mipitx/reg]0x14018084=0x00000333
[2520] [DISP][mipitx/reg]0x14018084=0x00010333
[2520] [DISP][mipitx/reg]0x14018084=0x00020333
[2520] [DISP][mipitx/reg]0x14018084=0x00100333
[2520] [DISP][mipitx/reg]0x14018084=0x00200333
[2540] [DISP][mipitx/reg]0x14018080=0x00000001
[2540] [DISP][mipitx/reg]0x14018050=0x00000000
[2540] [DISP][mipitx/reg]0x14018064=0x00000020
[2540] [DISP][mipitx/reg]0x14018040=0x00000882
[2540] [DISP][mipitx/reg]0x14018004=0x00000820
[2540] [DISP][mipitx/reg]0x14018008=0x00000400
[2540] [DISP][mipitx/reg]0x1401800c=0x00000100
[2540] [DISP][mipitx/reg]0x14018010=0x00000100
[2540] [DISP][mipitx/reg]0x14018014=0x00000100
[2540] [DISP][mipitx/reg]0x14018068=0x00000103
[2540] [DISP][mipitx/reg]0x14018068=0x00000102
[2540] [DISP][mipitx/reg]0x14018040=0x00000880
[2540] [DISP][mipitx/reg]0x14018000=0x00000401
[2540] [DISP][mipitx/reg]0x14018000=0x00000400
[2540] [DISP][mipitx/reg]0x14018044=0x88492481
[2540] [DISP][mipitx/reg]0x14018044=0x88492480
[2540] [DISP][mipitx/reg]0x14018050=0x00000000
[2540] [DISP][mipitx/reg]0x14018050=0x00000000
[2560] [DISP][mipitx/reg]0x14018050=0x00000000
[2560] [DISP][mipitx/reg]0x14018050=0x00000000
[2560] [DISP][mipitx/reg]0x14018054=0x00000000
[2560] [DISP][mipitx/reg]0x14018058=0x50000000
[2560] [DISP][mipitx/reg]0x14018080=0x00000000
[2560] [LK_DDP/ddp_manager]destroy path handle 0x41e69f40 on scenario display_interface
[2560] [LK_DDP/ddp_manager]release mutex 0 , left mutex 0x1f!
[2560] [LK_DDP/ddp_path]path disconnect on scenario display_interface
[2560] [LK_DDP/ddp_path]disconnect_path: ovl0 to dsi0
[2560] [LK_DDP/ddp_path]disconnect mout ovl0 to color0
[2560] [LK_DDP/ddp_path]disconnect mout dither to rdma0
[2560] [DISPCHECK]******** dump lcm driver information ********
[2560] [DISPCHECK][LCM], name: ili9881c_hd720_dsi_vdo_cpt
[2560] [DISPCHECK][LCM] resolution: 720 x 1280
[2580] [DISPCHECK][LCM] physical size: 0 x 0
[2580] [DISPCHECK][LCM] physical size: 0 x 0
[2580] [DISPCHECK][LCM] lcm_if:0, cmd_if:0
[2580] [DISPCHECK][LCM] interface: unknown
[2580] [DISPCHECK][LCM] Type: DSI
[2580] [DISPCHECK][LCM] DSI Mode: BURST_VDO_MODE
[2580] [DISPCHECK][LCM] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[2580] [DISPCHECK][LCM] vact: 8, vbp: 16, vfp: 16, vact_line: 1280, hact: 10, hbp: 80, hfp: 80, hblank: 0, hblank: 1105604892
[2580] [DISPCHECK][LCM] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[2580] [DISPCHECK][LCM] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 250, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[2580] [DISPCHECK][LCM] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[2580] [DISP]lcm handle is null, after probe:0x41e6a548
[2580] [DISP]^^ DISP_GetVRamSize: 13172736 bytes
[2580] mblock[0].start: 0x40000000, sz: 0x3ffc0000, limit: 0x100000000, max_addr: 0x0, max_rank: 0, target: -1, mblock[].rank: 0, reserved_addr: 0x7f330000,reserved_size: 0xc90000
[2600] mblock_reserve dbg[0]: 0, 1, 1, 1, 1
[2600] mblock_reserve: 7f330000 - 7ffc0000 from mblock 0
[2600] mblock-debug[0].start: 0x40000000, sz: 0x3f330000
[2600] FB base = 0x7f330000, FB size = 13172736
[2600] fb_va: 0x7f330000, fb_pa: 0x7f330000, fb_pa_k: 0x7f330000
[2600] [DISP]func|primary_display_init
[2600] [LK_DDP/ddp_manager]ddp manager init
[LK_ENV]get_env DFO
[2600] [DISP]env buffer = <null>
[2600] [DISP]env buffer = NULL
[2600] [DISP]LCM_FAKE_WIDTH = [DEC]0 [HEX]0x00000000
[2600] [DISP]LCM_FAKE_HEIGHT = [DEC]0 [HEX]0x00000000
[2600] [DISP]LCM Resolution will be changed, original: 720x1280, now: 0x0
[2600] [DISP]ERROR:Invalid resolution: 0x0
[2600] [DISP]ERROR:[DISP_DFO]WARNING!!! Change LCM Resolution FAILED!!!
[2600] [DISPCHECK]disp_lcm_probe SUCCESS
[2620] [DISP]func|disp_lcm_get_params
[2620] [DISP]func|_build_path_direct_link
[2620] [LK_DDP/ddp_manager]scenario primary_disp acquire mutex 0 , left mutex 0x1e!
[2620] [LK_DDP/ddp_manager]assign default irqs table index 0
[2620] [LK_DDP/ddp_manager]create handle 0x41e69f40 on scenario primary_disp
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module ovl0
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module color0
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module ccorr
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module aal
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module gamma
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module dither
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module rdma0
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module pwm0
[2620] [LK_DDP/ddp_manager] scenario primary_disp include module dsi0
[2640] [DISPCHECK]dpmgr create path SUCCESS(0x41e69f40)
[2640] [LK_DDP/ddp_manager]set dst module on scenario primary_disp, module dsi0
[2640] [LK_DDP/ddp_path]ddp_set_dst_module, scenario=primary_disp, dst_module=dsi0
[2640] [LK_DDP/ddp_path]dsi0 is already on path
[2640] [DISPCHECK]dpmgr set dst module FINISHED(dsi0 )
[2640] [LK_DDP/ddp_manager]path set lcm drv handle 0x41e69f40
[2640] [LK_DDP/ddp_manager]dsi0 set lcm utils
[2640] [DISPCHECK]primary display is DIRECT LINK MODE
[2640] [DISPCHECK]primary display BUILD cmdq trigger loop finished
[2640] [DISPCHECK]primary display START cmdq trigger loop finished
[2640] [DISP]func|disp_lcm_is_video_mode
[2640] [LK_DDP/ddp_manager]set scenario primary_disp mode Video Mode
[2640] [LK_DDP/ddp_manager]path init on scenario primary_disp
[2640] [LK_DDP/ddp_path]ddp path m4u off
[2640] [LK_DDP/ddp_path]ddp path top clock on
[2660] [LK_DDP/INFO]enable smi clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[2660] [LK_DDP/INFO]enable mutex clk, CG0 0xfffffffc, CG1 0xfffffffc, dummy CON = 0xfffffffc
[2660] [LK_DDP/ddp_path]ddp CG:fffffffc
[2660] [LK_DDP/ddp_path]mutex sof: dsi0 dst module dsi0 :vido_mode
[2660] [LK_DDP/ddp_path]module ovl0 added to mutex 0
[2660] [LK_DDP/ddp_path]module color0 added to mutex 0
[2660] [LK_DDP/ddp_path]module ccorr added to mutex 0
[2660] [LK_DDP/ddp_path]module aal added to mutex 0
[2660] [LK_DDP/ddp_path]module gamma added to mutex 0
[2660] [LK_DDP/ddp_path]module dither added to mutex 0
[2660] [LK_DDP/ddp_path]module rdma0 added to mutex 0
[2660] [LK_DDP/ddp_path]module pwm0 added to mutex 0
[2660] [LK_DDP/ddp_path]mutex 0 value=0x2f940, sof=dsi0
[2660] [LK_DDP/ddp_path]path connect on scenario primary_disp
[2660] [LK_DDP/ddp_path]connect_path: ovl0 to dsi0
[2680] [LK_DDP/ddp_path]connect mout ovl0 to color0 value 0x1
[2680] [LK_DDP/ddp_path]connect mout dither to rdma0 value 0x1
[2680] [LK_DDP/ddp_path]connect out_s rdma0 to dsi0 , bits=0x2
[2680] [LK_DDP/ddp_path]connect in_s ovl0 to color0 , bits=0x1
[2680] [LK_DDP/ddp_path]connect in_s rdma0 to dsi0 , bits=0x1
[2680] [LK_DDP/ddp_manager]scenario primary_disp init module ovl0
[2680] [LK_DDP/INFO]enable ovl0 clk, CG0 0xfffffbfc, CG1 0xfffffffc, dummy CON = 0xfffffbfc
[2680] [LK_DDP/OVL]OVL0Init open CG 0xfffffbfc
[2680] [LK_DDP/ddp_manager]scenario primary_disp init module color0
[2680] [LK_DDP/INFO]enable color0 clk, CG0 0xffffbbfc, CG1 0xfffffffc, dummy CON = 0xffffbbfc
[2680] [LK_DDP/ddp_manager]scenario primary_disp init module aal
[2680] [LK_DDP/INFO]enable aal clk, CG0 0xfffebbfc, CG1 0xfffffffc, dummy CON = 0xfffebbfc
[2680] [LK_DDP/ddp_manager]scenario primary_disp init module gamma
[2700] [LK_DDP/INFO]enable gamma clk, CG0 0xfffcbbfc, CG1 0xfffffffc, dummy CON = 0xfffcbbfc
[2700] [LK_DDP/ddp_manager]scenario primary_disp init module rdma0
[2700] [LK_DDP/INFO]enable rdma0 clk, CG0 0xfffcb3fc, CG1 0xfffffffc, dummy CON = 0xfffcb3fc
[2700] [LK_DDP/RDMA]RDMA0Init CG 0xfffcb3fc
[2700] [LK_DDP/ddp_manager]scenario primary_disp init module dsi0
[2700] [DISP]func|ddp_dsi_init
[2700] [LK_DDP/INFO]enable dsi0 clk, CG0 0xfffcb3fc, CG1 0xfffffff0, dummy CON = 0xfffcb3fc
[2700] [DISPCHECK]dsi0 init finished
[2700] [LK_DDP/ddp_manager]path config ovl 0, rdma 0, wdma 0, dst 1 on handle 0x41e69f40 scenario primary_disp
[2700] [LK_DDP/ddp_manager]scenario primary_disp config module ovl0
[2700] [LK_DDP/ddp_manager]scenario primary_disp config module color0
[2700] [LK_DDP/ddp_manager]scenario primary_disp config module aal
[2700] [LK_DDP/ddp_manager]scenario primary_disp config module gamma
[2720] [LK_DDP/ddp_manager]scenario primary_disp config module dither
[2720] [LK_DDP/ddp_manager]scenario primary_disp config module rdma0
[2720] [LK_DDP/RDMA]FIFO_VALID_Size = 0x020 = 32
[2720] [LK_DDP/RDMA]ultra_low_level = 0x06b = 107
[2720] [LK_DDP/RDMA]pre_ultra_low_level = 0x05f = 95
[2720] [LK_DDP/RDMA]pre_ultra_high_level = 0x06b = 107
[2720] [LK_DDP/RDMA]ultra_high_ofs = 0x001 = 1
[2720] [LK_DDP/RDMA]pre_ultra_low_ofs = 0x0a0 = 160
[2720] [LK_DDP/RDMA]pre_ultra_high_ofs = 0x001 = 1
[2720] [LK_DDP/ddp_manager]scenario primary_disp config module dsi0
[2720] [DISP]func|ddp_dsi_config
[2720] [DISPCHECK][DDPDSI] DSI Mode: BURST_VDO_MODE
[2720] [DISPCHECK][DDPDSI] LANE_NUM: 4,data_format: 0,vertical_sync_active: 0
[2720] [DISPCHECK][DDPDSI] vact: 8, vbp: 16, vfp: 16, vact_line: 1280, hact: 10, hbp: 80, hfp: 80, hblank: 0
[2720] [DISPCHECK][DDPDSI] pll_select: 0, pll_div1: 0, pll_div2: 0, fbk_div: 0,fbk_sel: 0, rg_bir: 0
[2740] [DISPCHECK][DDPDSI] rg_bic: 0, rg_bp: 0, PLL_CLOCK: 250, dsi_clock: 0, ssc_range: 0, ssc_disable: 0, compatibility_for_nvk: 0, cont_clock: 0
[2740] [DISPCHECK][DDPDSI] lcm_ext_te_enable: 0, noncont_clock: 0, noncont_clock_period: 0
[2740] [DISP]func|DSI_PHY_clk_setting
[2740] [DISP][mipitx/reg]0x14018044=0x88492481
[2740] [DISP][mipitx/reg]0x14018044=0x88492483
[2740] [DISP][mipitx/reg]0x14018040=0x00000882
[2740] [DISP][mipitx/reg]0x14018000=0x00000402
[2740] [DISP][mipitx/reg]0x14018000=0x00000403
[2740] [DISP][mipitx/reg]0x14018068=0x00000003
[2740] [DISP][mipitx/reg]0x14018068=0x00000101
[2740] [DISP][mipitx/reg]0x14018050=0x00000000
[2740] [DISP][mipitx/reg]0x14018050=0x00000000
[2740] [DISP][mipitx/reg]0x14018050=0x00000000
[2740] [DISP][mipitx/reg]0x14018054=0x00000001
[2740] [DISP][mipitx/reg]0x14018058=0x26000000
[2760] [DISP][mipitx/reg]0x14018058=0x26760000
[2760] [DISP][mipitx/reg]0x14018058=0x26762700
[2760] [DISP][mipitx/reg]0x14018058=0x26762762
[2760] [DISP][mipitx/reg]0x14018054=0x00000003
[2760] [DISP][mipitx/reg]0x14018054=0x01b10003
[2760] [DISP][mipitx/reg]0x1401805c=0x048b048b
[2760] [DISP][mipitx/reg]0x1401805c=0x048b048b
[2760] [DISP][dsi_drv.c] PLL config:data_rate=500,txdiv=1,pcw=645277538,delta1=5,pdelta1=0x48b
[2760] [DISP][mipitx/reg]0x14018054=0x01b10007
[2760] [DISP][mipitx/reg]0x14018004=0x00000821
[2760] [DISP][mipitx/reg]0x14018008=0x00000401
[2760] [DISP][mipitx/reg]0x1401800c=0x00000101
[2760] [DISP][mipitx/reg]0x14018010=0x00000101
[2760] [DISP][mipitx/reg]0x14018014=0x00000101
[2760] [DISP][mipitx/reg]0x14018050=0x00000001
[2760] [DISP][mipitx/reg]0x14018060=0x00000000
[2760] [DISP][mipitx/reg]0x14018060=0x00000001
[2760] [DISP][mipitx/reg]0x14018040=0x00000082
[2780] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, Cycle Time = 17(ns), Unit Interval = 3(ns). , lane# = 4
[2780] DISP/[DISP] - kernel - DSI_PHY_TIMCONFIG, HS_TRAIL = 120, HS_ZERO = 9, HS_PRPR = 4, LPX = 4, TA_GET = 20, TA_SURE = 6, TA_GO = 16, CLK_TRAIL = 6, CLK_ZERO = 23, CLK_HS_PRPR = 3
[2780] DSI_PHY_TIMCONFIG, 0x78090404,0x08140610,0x06170100,0x00080e03
[2780] [DISP]func|disp_lcm_init
[3060] [DISP][DSI] start: 0x00042902
[3060] [DISP][DSI] cmd: 0x038198ff
[3060] [DISP][DSI] size: 0x00000002
[3060] [DISP][DSI] start: 0x00011500
[3060] [DISP][DSI] size: 0x00000001
[3060] [DISP][DSI] start: 0x00021500
[3060] [DISP][DSI] size: 0x00000001
[3060] [DISP][DSI] start: 0x53031500
[3060] [DISP][DSI] size: 0x00000001
[3060] [DISP][DSI] start: 0x14041500
[3060] [DISP][DSI] size: 0x00000001
[3060] [DISP][DSI] start: 0x00051500
[3060] [DISP][DSI] size: 0x00000001
[3060] [DISP][DSI] start: 0x06061500
[3060] [DISP][DSI] size: 0x00000001
[3060] [DISP][DSI] start: 0x01071500
[3060] [DISP][DSI] size: 0x00000001
[3060] [DISP][DSI] start: 0x00081500
[3060] [DISP][DSI] size: 0x00000001
[3070] [DISP][DSI] start: 0x01091500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x190a1500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x010b1500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x000c1500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x000d1500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x000e1500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x190f1500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x19101500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x00111500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x00121500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x00131500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x00141500
[3080] [DISP][DSI] size: 0x00000001
[3080] [DISP][DSI] start: 0x00151500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x00161500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x00171500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x00181500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x00191500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x001a1500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x001b1500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x001c1500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x001d1500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x401e1500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x401f1500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x02201500
[3100] [DISP][DSI] size: 0x00000001
[3100] [DISP][DSI] start: 0x05211500
[3110] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x02221500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x00231500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x87241500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x87251500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x00261500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x00271500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x3b281500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x03291500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x002a1500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x002b1500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x002c1500
[3120] [DISP][DSI] size: 0x00000001
[3120] [DISP][DSI] start: 0x002d1500
[3120] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x002e1500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x002f1500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x00301500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x00311500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x00321500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x00331500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x04341500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x00351500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x00361500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x00371500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x01381500
[3140] [DISP][DSI] size: 0x00000001
[3140] [DISP][DSI] start: 0x01391500
[3140] [DISP][DSI] size: 0x00000001
[3150] [DISP][DSI] start: 0x403a1500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x403b1500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x003c1500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x003d1500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x003e1500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x003f1500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x00401500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x88411500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x00421500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x00431500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x00441500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x01501500
[3160] [DISP][DSI] size: 0x00000001
[3160] [DISP][DSI] start: 0x23511500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0x45521500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0x67531500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0x89541500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0xab551500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0x01561500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0x23571500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0x45581500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0x67591500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0x895a1500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0xab5b1500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0xcd5c1500
[3180] [DISP][DSI] size: 0x00000001
[3180] [DISP][DSI] start: 0xef5d1500
[3180] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x115e1500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x065f1500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x0c601500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x0d611500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x0e621500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x0f631500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x02641500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x02651500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x02661500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x02671500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x02681500
[3200] [DISP][DSI] size: 0x00000001
[3200] [DISP][DSI] start: 0x02691500
[3200] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x026a1500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x026b1500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x026c1500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x026d1500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x056e1500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x056f1500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x05701500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x02711500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x01721500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x00731500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x08741500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x08751500
[3220] [DISP][DSI] size: 0x00000001
[3220] [DISP][DSI] start: 0x0c761500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x0d771500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x0e781500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x0f791500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x027a1500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x027b1500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x027c1500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x027d1500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x027e1500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x027f1500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x02801500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x02811500
[3240] [DISP][DSI] size: 0x00000001
[3240] [DISP][DSI] start: 0x02821500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x02831500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x05841500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x05851500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x05861500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x02871500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x01881500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x00891500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x068a1500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x00042902
[3260] [DISP][DSI] cmd: 0x048198ff
[3260] [DISP][DSI] size: 0x00000002
[3260] [DISP][DSI] start: 0x156c1500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x396e1500
[3260] [DISP][DSI] size: 0x00000001
[3260] [DISP][DSI] start: 0x376f1500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0xa43a1500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0x1f8d1500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0xba871500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0x76261500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0xd1b22300
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0x00042902
[3280] [DISP][DSI] cmd: 0x018198ff
[3280] [DISP][DSI] size: 0x00000002
[3280] [DISP][DSI] start: 0x0a221500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0x9a531500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0xa5551500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0xb9501500
[3280] [DISP][DSI] size: 0x00000001
[3280] [DISP][DSI] start: 0xba511500
[3280] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x00311500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x14601500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x00611500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x1da01500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x21a11500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x31a21500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x0ea31500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x14a41500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x27a51500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x1ea61500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x1fa71500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x9fa81500
[3300] [DISP][DSI] size: 0x00000001
[3300] [DISP][DSI] start: 0x1aa91500
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x2caa1500
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x80ab1500
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x23ac1500
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x21ad1500
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x49ae1500
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x1daf1500
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x24b02300
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x50b12300
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x62b22300
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x39b32300
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x1dc02300
[3320] [DISP][DSI] size: 0x00000001
[3320] [DISP][DSI] start: 0x3cc12300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x48c22300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x17c32300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x15c42300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x28c52300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x19c62300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x1bc72300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0xb3c82300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x1bc92300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x24ca2300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0xb3cb2300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x11cc2300
[3340] [DISP][DSI] size: 0x00000001
[3340] [DISP][DSI] start: 0x0fcd2300
[3340] [DISP][DSI] size: 0x00000001
[3360] [DISP][DSI] start: 0x52ce2300
[3360] [DISP][DSI] size: 0x00000001
[3360] [DISP][DSI] start: 0x26cf2300
[3360] [DISP][DSI] size: 0x00000001
[3360] [DISP][DSI] start: 0x2dd02300
[3360] [DISP][DSI] size: 0x00000001
[3360] [DISP][DSI] start: 0x6dd12300
[3360] [DISP][DSI] size: 0x00000001
[3360] [DISP][DSI] start: 0x75d22300
[3360] [DISP][DSI] size: 0x00000001
[3360] [DISP][DSI] start: 0x39d32300
[3360] [DISP][DSI] size: 0x00000001
[3360] [DISP][DSI] start: 0x00042902
[3360] [DISP][DSI] cmd: 0x008198ff
[3360] [DISP][DSI] size: 0x00000002
[3360] [DISP][DSI] start: 0x00351500
[3360] [DISP][DSI] size: 0x00000001
[3360] [DISP][DSI] start: 0x00111500
[3360] [DISP][DSI] size: 0x00000001
[3600] [DISP][DSI] start: 0x00291500
[3600] [DISP][DSI] size: 0x00000001
[3620] [DISP]func|DSI_set_cmdq
[3620] [DISPCHECK]DSI_set_cmdq, module=dsi0 , cmdq=0x00000000
[3620] [DISP] - kernel - DSI_set_cmdq. DSI_CMDQ+0000 : 0x00013700
[3620] [DISP]read lcm maximum return size failed.
[3620] [DISP]func|DSI_dcs_read_lcm_reg_v2
[3620] DISP/ Start polling DSI read ready!!!
[3660] DISP/ Polling DSI read ready timeout!!!
[3680] DSI0 state:Waiting RX-read data
[3680] DSI Mode: lane num: transfer count: status: [3680] ---------- Start dump DSI0 registers ----------
[3680] DSI+0000 : 0x00000001 0x00000000 0x00000000 0x80000000
[3680] DSI+0010 : 0x00000000 0x00000000 0x0000007c 0x00030870
[3680] DSI+0020 : 0x00000008 0x00000010 0x00000010 0x00000500
[3680] DSI+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[3680] DSI+0040 : 0x00000000 0x00000000 0x00000000 0x00000000
[3680] DSI+0050 : 0x0000001c 0x00000104 0x000000e4 0x00000000
[3680] DSI+0060 : 0x00000001 0x00010000 0x00000000 0x00000000
[3680] DSI+0070 : 0x00000000 0x00000000 0x00000000 0x00000000
[3680] DSI+0080 : 0x00000000 0x00000000 0x00000020 0x00000000
[3680] DSI+0090 : 0x0000003c 0x00000000 0x00000000 0x00000000
[3680] DSI+00a0 : 0x00060080 0x00002000 0x00000000 0x00000000
[3680] DSI+00b0 : 0x00000000 0x00000000 0x00000000 0x00000000
[3700] DSI+00c0 : 0x00000000 0x00000000 0x00000000 0x00000000
[3700] DSI+00d0 : 0x00000000 0x00000000 0x00000000 0x00000000
[3700] DSI+00e0 : 0x00000000 0x00000000 0x00000000 0x00000000
[3700] DSI+00f0 : 0x00000000 0x00000000 0x00000000 0x00000000
[3700] DSI+0100 : 0x00000055 0x00000000 0x00000000 0x000000b8
[3700] DSI+0110 : 0x78090404 0x08140610 0x06170100 0x00080e03
[3700] DSI+0120 : 0x00000000 0x00000000 0x00000000 0x00000000
[3700] DSI+0130 : 0x00000021 0x00000000 0x00000000 0x00000000
[3700] DSI+0140 : 0x00000000 0x00000000 0x00010001 0x01010100
[3700] DSI+0150 : 0x01080001 0x01010101 0x00000101 0x10000000
[3700] DSI+0160 : 0x00010200 0x00000001 0x00000000 0x00000000
[3700] DSI+0170 : 0x00000000 0xfff00000 0x00000000 0x00200000
[3700] DSI_CMD+0000 : 0x000a0604 0x008198ff 0x00000104 0x65c96dc6
[3700] DSI_CMD+0010 : 0x1fb52006 0x60160a3e 0xd9e50d77 0x5c42a90f
[3720] DSI_CMD+0020 : 0x787b9491 0x28f55582 0x10657df7 0xe3f39022
[3720] DSI_CMD+0030 : 0x2838feb6 0x9cb8d0d0 0x69527205 0xf6b5d582
[3720] DSI_CMD+0040 : 0xa2ee65c0 0xd474745e 0x11cfefd0 0xd1d41e17
[3720] DSI_CMD+0050 : 0x705d471d 0x57491712 0x5fc7505e 0xd27597c7
[3720] DSI_CMD+0060 : 0x5af0125b 0x5f53104f 0xd51b97fb 0x8e2651ad
[3720] DSI_CMD+0070 : 0xd736f643 0x8124585e 0x1f52c105 0xdd949d95
[3720] DSI_CMD+0080 : 0x4712c353 0xc6800d11 0x84554fb7 0xebd45444
[3720] DSI_CMD+0090 : 0x4b067445 0x84751146 0x733f15bd 0x19936d6f
[3720] DSI_CMD+00a0 : 0xb3530de1 0x0d17e508 0x4a246d30 0x6551df1c
[3720] DSI_CMD+00b0 : 0x42686bd1 0xf9287cf8 0xd37f0991 0xdacd707a
[3720] DSI_CMD+00c0 : 0x9cdb8955 0x1f82e1ce 0x20f0f876 0xbb17fd0e
[3720] DSI_CMD+00d0 : 0x533b98ba 0x04535bdc 0xe79a65ff 0x3421dbb1
[3720] DSI_CMD+00e0 : 0xefb40d55 0x1cdde64f 0x3f575591 0x521bd001
[3740] DSI_CMD+00f0 : 0x232d15d5 0x45572548 0xa4c47f4d 0x14749f66
[3740] DSI_CMD+0100 : 0x735f78cf 0x44fb44e5 0x57ec5513 0xf96a4dd8
[3740] DSI_CMD+0110 : 0xb8411748 0x79754808 0xae674c55 0x77d36f37
[3740] DSI_CMD+0120 : 0x91711452 0x559d6c32 0x96cc3dad 0x039aa1d2
[3740] DSI_CMD+0130 : 0x557d7205 0x8edd7656 0x278375e5 0xcd5fd157
[3740] DSI_CMD+0140 : 0x575cd67d 0xdc3c4919 0xe1d93340 0x9169999b
[3740] DSI_CMD+0150 : 0x419ed5d8 0xf26fcd50 0x73f50cc1 0xa8096178
[3740] DSI_CMD+0160 : 0xa6735b55 0x42d93d56 0x71d674db 0xbcd18bfd
[3740] DSI_CMD+0170 : 0xc7f817c8 0x5d75c925 0xf6b59901 0xd33735b9
[3740] DSI_CMD+0180 : 0xb55dd961 0x371417e8 0xd9596103 0x9e6bf1f1
[3740] DSI_CMD+0190 : 0x14d91fd5 0x08c30938 0x55478378 0x4eb22503
[3740] DSI_CMD+01a0 : 0xdd572651 0x179d3d1f 0xfbd09750 0xdfbf9407
[3740] DSI_CMD+01b0 : 0x92d1e931 0x9ad8cf8b 0x94e0e442 0x9a79b5d5
[3740] DSI_CMD+01c0 : 0x45a4f911 0xa5a53535 0x6031c351 0x57967a81
[3760] DSI_CMD+01d0 : 0x1b172371 0x142c5772 0x08097093 0xb198451c
[3760] DSI_CMD+01e0 : 0x5dd3c66e 0x43966fd5 0x50047605 0xf3477857
[3760] DSI_CMD+01f0 : 0x4cb1d7e7 0xf7312d59 0xa7f44f01 0xf2104578
[3760] DSI_PHY+0000 : 0x00000403 0x00000821 0x00000401 0x00000101
[3760] DSI_PHY+0010 : 0x00000101 0x00000101 0x00000000 0x00000000
[3760] DSI_PHY+0020 : 0x00000000 0x00000000 0x00000000 0x00000000
[3760] DSI_PHY+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[3760] DSI_PHY+0040 : 0x00000082 0x88492483 0x00000000 0x00000000
[3760] DSI_PHY+0050 : 0x00000001 0x01b10007 0x26762762 0x048b048b
[3760] DSI_PHY+0060 : 0x00000001 0x00000020 0x00000101 0x00000000
[3760] DSI_PHY+0070 : 0x00000000 0x00000000 0x00000000 0x00043210
[3760] DSI_PHY+0080 : 0x00000000 0x00000333 0x00000000 0x00000000
[3760] DSI_PHY+0090 : 0x00000000 0x00000000 0x00000000 0x00000000
[3780] [DISP]lcm is not connected
[3780] [DISP]func|disp_lcm_is_video_mode
[3780] [LK_DDP/ddp_manager]map event 7 to irq 0x20004 on scenario primary_disp
[3780] [LK_DDP/ddp_manager]enable event on scenario primary_disp, event 7, irtbit 0x20004
[3780] [LK_DDP/ddp_manager]enable event on scenario primary_disp, event 1, irtbit 0x20004
[3780] [DISP]func|primary_display_config_input
[3780] [LK_DDP/ddp_manager]path check busy on scenario primary_disp
[3780] [DISP]func|ddp_dsi_is_busy
[3800] [LK_DDP/ddp_manager]path config ovl 1, rdma 0, wdma 0, dst 0 on handle 0x41e69f40 scenario primary_disp
[3800] [LK_DDP/ddp_manager]scenario primary_disp config module ovl0
[3800] [LK_DDP/OVL]module 0, layer=3, en=1, src=0, fmt=16785410, addr=0x7f6c8000, x=0, y=0, pitch=2880, dst(0, 0, 720, 1280),keyEn=0, key=0, aen=1, alpha=255
[3800] [LK_DDP/OVL]ovl0, layer=3, source=memory, off(x=0, y=0), dst(0, 0, 720, 1280),pitch=2880,fmt=eBGRA8888, addr=7f6c8000, keyEn=0, key=0, aen=1, alpha=255
[3800] [LK_DDP/ddp_manager]scenario primary_disp config module color0
[3800] [LK_DDP/ddp_manager]scenario primary_disp config module aal
[3800] [LK_DDP/ddp_manager]scenario primary_disp config module gamma
[3800] [LK_DDP/ddp_manager]scenario primary_disp config module dither
[3800] [LK_DDP/ddp_manager]scenario primary_disp config module rdma0
[3800] [LK_DDP/ddp_manager]scenario primary_disp config module dsi0
[3820] [DISP]func|ddp_dsi_config
[3820] [DISP]func|primary_display_config_input
[3820] [LK_DDP/ddp_manager]path check busy on scenario primary_disp
[3820] [DISP]func|ddp_dsi_is_busy
[3820] [LK_DDP/ddp_manager]path config ovl 1, rdma 0, wdma 0, dst 0 on handle 0x41e69f40 scenario primary_disp
[3820] [LK_DDP/ddp_manager]scenario primary_disp config module ovl0
[3820] [LK_DDP/OVL]module 0, layer=0, en=1, src=0, fmt=16785410, addr=0x7f330000, x=0, y=0, pitch=2944, dst(0, 0, 720, 1280),keyEn=0, key=0, aen=1, alpha=255
[3820] [LK_DDP/OVL]ovl0, layer=0, source=memory, off(x=0, y=0), dst(0, 0, 720, 1280),pitch=2944,fmt=eBGRA8888, addr=7f330000, keyEn=0, key=0, aen=1, alpha=255
[3820] [LK_DDP/OVL]module 0, layer=3, en=1, src=0, fmt=16785410, addr=0x7f6c8000, x=0, y=0, pitch=2880, dst(0, 0, 720, 1280),keyEn=0, key=0, aen=1, alpha=255
[3820] [LK_DDP/OVL]ovl0, layer=3, source=memory, off(x=0, y=0), dst(0, 0, 720, 1280),pitch=2880,fmt=eBGRA8888, addr=7f6c8000, keyEn=0, key=0, aen=1, alpha=255
[3840] [LK_DDP/ddp_manager]scenario primary_disp config module color0
[3840] [LK_DDP/ddp_manager]scenario primary_disp config module aal
[3840] [LK_DDP/ddp_manager]scenario primary_disp config module gamma
[3840] [LK_DDP/ddp_manager]scenario primary_disp config module dither
[3840] [LK_DDP/ddp_manager]scenario primary_disp config module rdma0
[3840] [LK_DDP/ddp_manager]scenario primary_disp config module dsi0
[3840] [DISP]func|ddp_dsi_config
[3840] [lk logo: mt_disp_fill_rect 309]
[3840] [lk logo: init_fb_screen 67]
[3840] mt_get_logo_db_addr: 0x7ef30000
[3840] [lk logo: init_fb_screen 85]MTK_LCM_PHYSICAL_ROTATION = 0
[3840] [lk logo: sync_anim_version 50]
[3840] [lk logo: init_fb_screen 108]pinfo[0]=0xffffffff, pinfo[1]=0xffffffff, pinfo[2]=-1
[3840] [lk logo: init_fb_screen 110]define ANIMATION_NEW:show new animation with capacity num
[3860] [lk logo: init_fb_screen 111]CAPACITY_LEFT =278, CAPACITY_TOP =556
[3860] [lk logo: init_fb_screen 112]LCM_HEIGHT=441, LCM_WIDTH=817
[3860] [show_logo_common: fill_rect_with_color_by_32bit 341]
[3960] fb dump: 0x00000000, 0x00000000, 0x00000000, 0x00000000
[3960] [DISP]func|primary_display_trigger
[3960] [LK_DDP/ddp_manager]path check busy on scenario primary_disp
[3960] [DISP]func|ddp_dsi_is_busy
[3960] [DISPCHECK]trigger mode: DIRECT_LINK
[3960] [DISP]func|disp_lcm_is_video_mode
[3960] [LK_DDP/ddp_manager]path start on scenario primary_disp
[3960] [LK_DDP/ddp_manager]scenario primary_disp start module ovl0
[3960] [LK_DDP/ddp_manager]scenario primary_disp start module rdma0
[3960] [LK_DDP/ddp_manager]scenario primary_disp start module dsi0
[3960] [LK_DDP/ddp_manager]dpmgr_path_trigger on scenario primary_disp
[3980] [LK_DDP/ddp_path]mutex 0 enable
[3980] [LK_DDP/ddp_manager]dsi0 trigger
[3980] [LK_DDP/ddp_manager]check status on scenario primary_disp, module_num 9
[3980] [LK_DDP/ddp_path]path check path on scenario primary_disp
[3980] [LK_DDP/ddp_path]check_path: ovl0 to dsi0
[3980] [LK_DDP/ddp_path]path: ovl0 to dsi0 is connected
[3980] [LK_DDP/ddp_path]check mutex 0 on scenario primary_disp
[3980] [LK_DDP/ddp_path]mutex sof: dsi0 dst module dsi0 :vido_mode
[3980] [LK_DDP/OVL]==DISP OVL0 ANALYSIS==
[3980] [LK_DDP/OVL]ovl_en=1,layer_enable(1,0,0,1),bg(w=720, h=1280),cur_pos(x=329,y=361),layer_hit(1,0,0,1)
[3980] [LK_DDP/OVL]layer0: w=720,h=1280,off(x=0,y=0),pitch=2944,addr=0x7f330000,fmt=eBGRA8888, source=memory
[3980] [LK_DDP/OVL]ovl rdma0 status:(en 7929857)
[3980] [LK_DDP/OVL]layer3: w=720,h=1280,off(x=0,y=0),pitch=2880,addr=0x7f6c8000,fmt=eBGRA8888, source=memory
[3980] [LK_DDP/OVL]ovl rdma3 status:(en 7798785)
[4000] [LK_DDP/DUMP]==DISP COLOR0 ANALYSIS==
[4000] [LK_DDP/DUMP]color0: bypass=1, w=720, h=1280, pixel_cnt=0, line_cnt=0,
[4000] [LK_DDP/DUMP]ccorr: en=1, config=1, w=720, h=1280, in_p_cnt=501, in_l_cnt=849, out_p_cnt=543, out_l_cnt=849
[4000] [LK_DDP/DUMP]==DISP AAL ANALYSIS==
[4000] [LK_DDP/DUMP]aal: bypass=1, relay=1, en=0, w=720, h=1280
[4000] [LK_DDP/DUMP]==DISP GAMMA ANALYSIS==
[4000] [LK_DDP/DUMP]gamma: en=0, w=720, h=1280, in_p_cnt=1, in_l_cnt=1, out_p_cnt=1, out_l_cnt=1
[4000] [LK_DDP/DUMP]dither: en=1, config=2, w=720, h=1280, in_p_cnt=569, in_l_cnt=1174, out_p_cnt=604, out_l_cnt=1174
[4000] [LK_DDP/RDMA]==DISP RDMA0 ANALYSIS==
[4000] [LK_DDP/RDMA]rdma0: en=1, w=720, h=1280, pitch=0, addr=0x0, fmt=rgb565, fifo_min=13, in_p_cnt=16, in_l_cnt=2, out_p_cnt=68, out_l_cnt=0
[4000] [LK_DDP/DUMP]==DISP PWM0 ANALYSIS==
[4000] [LK_DDP/DUMP]pwm clock=0
[4000] [LK_DDP/DUMP]==DISP MMSYS_CONFIG ANALYSIS==
[4020] [LK_DDP/DUMP]mmsys clock=0x0, CG_CON0=0xfffcb3fc, CG_CON1=0xfffffff0
[4020] [LK_DDP/DUMP]clock on modules:smi_common, smi_larb0, ovl0, ovl1, wdma0, ccorr, aal, disp_pwm_mm, disp_pwm_26m, dsi_engine, dsi_digital,
[4020] [LK_DDP/DUMP]valid0=0x40093fb, valid1=0x0, ready0=0x0, ready1=0x400000, greq=00
[4020] [LK_DDP/DUMP]ovl0_mm_ovl0_mout :Valid,-
[4020] [LK_DDP/DUMP]ovl0_mout0_mm_color_sin1 :Valid,-
[4020] [LK_DDP/DUMP]ovl0_mout1_mm_wdma0_sin0 :--
[4020] [LK_DDP/DUMP]color_sel_mm_color :Valid,-
[4020] [LK_DDP/DUMP]color_mm_ccorr :Valid,-
[4020] [LK_DDP/DUMP]ccorr_mm_aal :Valid,-
[4020] [LK_DDP/DUMP]aal_mm_gamma :Valid,-
[4020] [LK_DDP/DUMP]gamma_mm_dither :Valid,-
[4020] [LK_DDP/DUMP]dither_mm_dither_mout :Valid,-
[4020] [LK_DDP/DUMP]dither_mout0_mm_rdma0 :Valid,-
[4020] [LK_DDP/DUMP]dither_mout1_mm_ufoe_sin1 :--
[4040] [LK_DDP/DUMP]dither_mout2_mm_wdma0_sin1:--
[4040] [LK_DDP/DUMP]rdma0_mm_rdma0_sout :Valid,-
[4040] [LK_DDP/DUMP]rdma0_sout0_mm_ufoe_sin0 :--
[4040] [LK_DDP/DUMP]rdma0_sout1_mm_color_sin0 :--
[4040] [LK_DDP/DUMP]rdma0_sout2_mm_dsi0_sin1 :Valid,-
[4040] [LK_DDP/DUMP]rdma0_sout3_mm_dpi0_sin1 :--
[4040] [LK_DDP/DUMP]ufoe_sel_mm_ufoe :--
[4040] [LK_DDP/DUMP]ufoe_mm_ufoe_mout :--
[4040] [LK_DDP/DUMP]ufoe_mout0_mm_dsi0_sin0 :--
[4040] [LK_DDP/DUMP]ufoe_mout1_mm_dpi0_sin0 :--
[4040] [LK_DDP/DUMP]ufoe_mout2_mm_wdma0_sin2 :--
[4040] [LK_DDP/DUMP]wdma0_sel_mm_wdma0 :--
[4040] [LK_DDP/DUMP]ovl1_mm_ovl1_mout :--
[4040] [LK_DDP/DUMP]ovl1_mout0_mm_rdma1 :--
[4040] [LK_DDP/DUMP]ovl1_mout1_mm_wdma1 :--
[4040] [LK_DDP/DUMP]ovl1_mout2_mm_ovl0 :Valid,-
[4040] [LK_DDP/DUMP]rdma1_mm_rdma1_sout :--
[4040] [LK_DDP/DUMP]rdma1_sout0_mm_dsi0_sin2 :--
[4060] [LK_DDP/DUMP]rdma1_sout1_mm_dpi0_sin2 :--
[4060] [LK_DDP/DUMP]dis0_sel_mm_dsi0 :--
[4060] [LK_DDP/DUMP]dpi0_sel_mm_dpi0 :--
[4060] [LK_DDP/DUMP]==DISP Mutex Analysis==
[4060] [LK_DDP/DUMP]MUTEX0 :mode=dsi0_vdo,module=(ovl0,rdma1,color0,aal,gamma,dither,reserved,mutex-unknown,)
[4060] [LK_DDP/OVL]== DISP OVL0 ==
[4060] [LK_DDP/OVL](0x000)O_STA =0xd
[4060] [LK_DDP/OVL](0x004)O_INTEN =0xe
[4060] [LK_DDP/OVL](0x008)O_INTSTA =0x3
[4060] [LK_DDP/OVL](0x00c)O_EN =0x1
[4060] [LK_DDP/OVL](0x010)O_TRIG =0x0
[4060] [LK_DDP/OVL](0x014)O_RST =0x0
[4060] [LK_DDP/OVL](0x020)O_ROI_SIZE =0x50002d0
[4060] [LK_DDP/OVL](0x024)O_PATH_CON =0x60000001
[4060] [LK_DDP/OVL](0x028)O_ROI_BGCLR =0x0
[4060] [LK_DDP/OVL](0x02c)O_SRC_CON =0x9
[4060] [LK_DDP/OVL](0x030)O0_CON =0x21ff
[4060] [LK_DDP/OVL](0x034)O0_SRCKEY =0x0
[4070] [LK_DDP/OVL](0x038)O0_SRC_SIZE =0x50002d0
[4080] [LK_DDP/OVL](0x03c)O0_OFFSET =0x0
[4080] [LK_DDP/OVL](0xf40)O0_ADDR =0x7f330000
[4080] [LK_DDP/OVL](0x044)O0_PITCH =0xff0b80
[4080] [LK_DDP/OVL](0x048)O0_TILE =0x0
[4080] [LK_DDP/OVL](0x0c0)O0_R_CTRL =0x6c0001
[4080] [LK_DDP/OVL](0x0c8)O0_R_M_GMC_SET1 =0x6070
[4080] [LK_DDP/OVL](0x0cc)O0_R_M_SLOW_CON =0x0
[4080] [LK_DDP/OVL](0x0d0)O0_R_FIFO_CTRL =0x800000
[4080] [LK_DDP/OVL](0x24c)O0_R_DBG =0x60000001
[4080] [LK_DDP/OVL](0x090)O3_CON =0x21ff
[4080] [LK_DDP/OVL](0x094)O3_SRCKEY =0x0
[4080] [LK_DDP/OVL](0x098)O3_SRC_SIZE =0x50002d0
[4080] [LK_DDP/OVL](0x09c)O3_OFFSET =0x0
[4080] [LK_DDP/OVL](0xfa0)O3_ADDR =0x7f6c8000
[4080] [LK_DDP/OVL](0x0a4)O3_PITCH =0xff0b40
[4080] [LK_DDP/OVL](0x0a8)O3_TILE =0x0
[4080] [LK_DDP/OVL](0x120)O3_R_CTRL =0x760001
[4080] [LK_DDP/OVL](0x128)O3_R_M_GMC_SET1 =0x6070
[4080] [LK_DDP/OVL](0x12c)O3_R_M_SLOW_CON =0x0
[4100] [LK_DDP/OVL](0x130)O3_R_FIFO_CTRL =0x800000
[4100] [LK_DDP/OVL](0x258)O3_R_DBG =0x30000001
[4100] [LK_DDP/OVL](0x1d4)O_DBG_MON_SEL =0x0
[4100] [LK_DDP/OVL](0x200)O_DUMMY_REG =0x0
[4100] [LK_DDP/OVL](0x240)O_FLOW_CTRL =0x8061020
[4100] [LK_DDP/OVL](0x244)O_ADDCON =0x845b4029
[4100] [LK_DDP/DUMP]==DISP COLOR0 REGS==
[4100] [LK_DDP/DUMP](0x400)COLOR_CFG_MAIN =0x209c
[4100] [LK_DDP/DUMP](0x404)COLOR_PXL_CNT_MAIN =0x0
[4100] [LK_DDP/DUMP](0x408)COLOR_LINE_CNT_MAIN =0x0
[4100] [LK_DDP/DUMP](0xc00)COLOR_START =0x3
[4100] [LK_DDP/DUMP](0xc50)COLOR_INTER_IP_W =0x2d0
[4100] [LK_DDP/DUMP](0xc54)COLOR_INTER_IP_H =0x500
[4100] [LK_DDP/DUMP]==DISP CCORR REGS==
[4100] [LK_DDP/DUMP](00)EN =0x1
[4100] [LK_DDP/DUMP](20)CFG =0x1
[4100] [LK_DDP/DUMP](24)IN_CNT =0x107001f
[4100] [LK_DDP/DUMP](28)OUT_CNT =0x12d001b
[4100] [LK_DDP/DUMP](30)SIZE =0x2d00500
[4120] [LK_DDP/DUMP]==DISP AAL REGS==
[4120] [LK_DDP/DUMP](0x000)AAL_EN =0x0
[4120] [LK_DDP/DUMP](0x008)AAL_INTEN =0x0
[4120] [LK_DDP/DUMP](0x00c)AAL_INTSTA =0x0
[4120] [LK_DDP/DUMP](0x020)AAL_CFG =0x1
[4120] [LK_DDP/DUMP](0x024)AAL_IN_CNT =0x10001
[4120] [LK_DDP/DUMP](0x028)AAL_OUT_CNT =0x10001
[4120] [LK_DDP/DUMP](0x030)AAL_SIZE =0x2d00500
[4120] [LK_DDP/DUMP](0x20c)AAL_CABC_00 =0x0
[4120] [LK_DDP/DUMP](0x214)AAL_CABC_02 =0x100
[4120] [LK_DDP/DUMP](0x20c)AAL_STATUS_00 =0x0
[4120] [LK_DDP/DUMP](0x210)AAL_STATUS_01 =0x0
[4120] [LK_DDP/DUMP](0x2a0)AAL_STATUS_31 =0x0
[4120] [LK_DDP/DUMP](0x2a4)AAL_STATUS_32 =0x3fffff
[4120] [LK_DDP/DUMP](0x3b0)AAL_DRE_MAPPING_00 =0x18
[4120] [LK_DDP/DUMP]==DISP GAMMA REGS==
[4120] [LK_DDP/DUMP](0x000)GA_EN =0x0
[4120] [LK_DDP/DUMP](0x004)GA_RESET =0x0
[4120] [LK_DDP/DUMP](0x008)GA_INTEN =0x0
[4140] [LK_DDP/DUMP](0x00c)GA_INTSTA =0x0
[4140] [LK_DDP/DUMP](0x010)GA_STATUS =0xa0
[4140] [LK_DDP/DUMP](0x020)GA_CFG =0x0
[4140] [LK_DDP/DUMP](0x024)GA_IN_COUNT =0x10001
[4140] [LK_DDP/DUMP](0x028)GA_OUT_COUNT =0x10001
[4140] [LK_DDP/DUMP](0x02c)GA_CHKSUM =0x0
[4140] [LK_DDP/DUMP](0x030)GA_SIZE =0x2d00500
[4140] [LK_DDP/DUMP](0x0c0)GA_DUMMY_REG =0x0
[4140] [LK_DDP/DUMP](0x800)GA_LUT =0x10c229eb
[4140] [LK_DDP/DUMP]==DISP DITHER REGS==
[4140] [LK_DDP/DUMP](00)EN =0x1
[4140] [LK_DDP/DUMP](20)CFG =0x2
[4140] [LK_DDP/DUMP](24)IN_CNT =0x180013b
[4140] [LK_DDP/DUMP](28)OUT_CNT =0x1a601c6
[4140] [LK_DDP/DUMP](30)SIZE =0x2d00500
[4140] [LK_DDP/RDMA]== DISP RDMA0 ==
[4140] [LK_DDP/RDMA](0x000)R_INTEN =0x3f
[4140] [LK_DDP/RDMA](0x004)R_INTS =0x26
[4140] [LK_DDP/RDMA](0x010)R_CON =0x101
[4140] [LK_DDP/RDMA](0x014)R_SIZE0 =0x2d0
[4160] [LK_DDP/RDMA](0x018)R_SIZE1 =0x500
[4160] [LK_DDP/RDMA](0x01c)R_TAR_LINE =0xf0
[4160] [LK_DDP/RDMA](0x024)R_M_CON =0x0
[4160] [LK_DDP/RDMA](0xf00)R_M_S_ADDR =0x0
[4160] [LK_DDP/RDMA](0x02c)R_M_SRC_PITCH =0x0
[4160] [LK_DDP/RDMA](0x030)R_M_GMC_SET0 =0x1a01356b
[4160] [LK_DDP/RDMA](0x034)R_M_SLOW_CON =0x0
[4160] [LK_DDP/RDMA](0x038)R_M_GMC_SET1 =0x10
[4160] [LK_DDP/RDMA](0x040)R_FIFO_CON =0x81000010
[4160] [LK_DDP/RDMA](0x044)R_FIFO_LOG =0xd
[4160] [LK_DDP/RDMA](0x078)R_PRE_ADD0 =0x0
[4160] [LK_DDP/RDMA](0x07c)R_PRE_ADD1 =0x0
[4160] [LK_DDP/RDMA](0x080)R_PRE_ADD2 =0x0
[4160] [LK_DDP/RDMA](0x084)R_POST_ADD0 =0x0
[4160] [LK_DDP/RDMA](0x088)R_POST_ADD1 =0x0
[4160] [LK_DDP/RDMA](0x08c)R_POST_ADD2 =0x0
[4160] [LK_DDP/RDMA](0x090)R_DUMMY =0xfff00000
[4160] [LK_DDP/RDMA](0x094)R_OUT_SEL =0x0
[4160] [LK_DDP/RDMA](0x094)R_M_START =0x0
[4180] [LK_DDP/DUMP]==DISP PWM0 REGS==
[4180] [LK_DDP/DUMP](0x000)PWM_EN =0x0
[4180] [LK_DDP/DUMP](0x008)PWM_CON_0 =0x0
[4180] [LK_DDP/DUMP](0x010)PWM_CON_1 =0x3ff
[4180] [LK_DDP/DUMP](0x028)PWM_DEBUG =0x0
[4180] [LK_DDP/DUMP]==DISP DSI0 REGS==
[4180] [LK_DDP/DUMP]DSI0+0000 : 0x00000001 0x00000000 0x00000000 0x80000710
[4180] [LK_DDP/DUMP]DSI0+0010 : 0x00000000 0x00000003 0x0000007c 0x00030870
[4180] [LK_DDP/DUMP]DSI0+0020 : 0x00000008 0x00000010 0x00000010 0x00000500
[4180] [LK_DDP/DUMP]DSI0+0030 : 0x00000000 0x00000000 0x00000000 0x00000000
[4180] [LK_DDP/DUMP]DSI0+0040 : 0x00000000 0x00000000 0x00000000 0x00000000
[4180] [LK_DDP/DUMP]DSI0+0050 : 0x0000001c 0x00000104 0x000000e4 0x00000000
[4180] [LK_DDP/DUMP]DSI0+0060 : 0x00000001 0x00010000 0x00000000 0x00000000
[4180] [LK_DDP/DUMP]DSI0+0070 : 0x00000000 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+0080 : 0x00000000 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+0090 : 0x0000003c 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+00a0 : 0x00060080 0x00002000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+00b0 : 0x00000000 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+00c0 : 0x00000000 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+00d0 : 0x00000000 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+00e0 : 0x00000000 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+00f0 : 0x00000000 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+0100 : 0x00000055 0x00000001 0x00000000 0x000000b8
[4200] [LK_DDP/DUMP]DSI0+0110 : 0x78090404 0x08140610 0x06170100 0x00080e03
[4200] [LK_DDP/DUMP]DSI0+0120 : 0x00000000 0x00000000 0x00000000 0x00000000
[4200] [LK_DDP/DUMP]DSI0+0130 : 0x00000021 0x00000000 0x00000000 0x00000000
[4220] [LK_DDP/DUMP]== DISP Config ==
[4220] [LK_DDP/DUMP](0x0 )MMSYS_INTEN =0x0
[4220] [LK_DDP/DUMP](0x4 )MMSYS_INTSTA =0x0
[4220] [LK_DDP/DUMP](0xc )PWM_APB_ERR_ADDR =0x0
[4220] [LK_DDP/DUMP](0x30)OVL0_MOUT_EN =0x1
[4220] [LK_DDP/DUMP](0x38)DITHER_MOUT_EN =0x1
[4220] [LK_DDP/DUMP](0x3C)UFOE_MOUT_EN =0x0
[4220] [LK_DDP/DUMP](0x40)MMSYS_MOUT_RST =0x0
[4220] [LK_DDP/DUMP](0x58)COLOR0_SIN =0x1
[4220] [LK_DDP/DUMP](0x5C)WDMA0_SIN =0x0
[4220] [LK_DDP/DUMP](0x60)UFOE_SIN =0x0
[4220] [LK_DDP/DUMP](0x64)DSI0_SIN =0x1
[4220] [LK_DDP/DUMP](0x68)DPI0_SIN =0x0
[4220] [LK_DDP/DUMP](0x6C)RDMA0_SOUT_SIN =0x2
[4220] [LK_DDP/DUMP](0x70)RDMA1_SOUT_SIN =0x0
[4220] [LK_DDP/DUMP](0x0F0)MM_MISC =0x0
[4220] [LK_DDP/DUMP](0x100)MM_CG_CON0 =0xfffcb3fc
[4220] [LK_DDP/DUMP](0x110)MM_CG_CON1 =0xfffffff0
[4230] [LK_DDP/DUMP](0x120)MM_HW_DCM_DIS0 =0x0
[4240] [LK_DDP/DUMP](0x140)MM_SW0_RST_B =0xffffffff
[4240] [LK_DDP/DUMP](0x144)MM_SW1_RST_B =0xffffffff
[4240] [LK_DDP/DUMP](0x150)MM_LCM_RST_B =0x1
[4240] [LK_DDP/DUMP](0x880)MM_DBG_OUT_SEL =0x0
[4240] [LK_DDP/DUMP](0x890)MM_DUMMY =0xfffcb3fc
[4240] [LK_DDP/DUMP](0x8a0)DISP_VALID_0 =0x40093fb
[4240] [LK_DDP/DUMP](0x8a8)DISP_READY_0 =0x4009300
[4240] [LK_DDP/DUMP]==DISP MUTEX REGS==
[4240] [LK_DDP/DUMP](0x000)M_INTEN =0x0
[4240] [LK_DDP/DUMP](0x004)M_INTSTA =0x401
[4240] [LK_DDP/DUMP](0x020)M0_EN =0x1
[4240] [LK_DDP/DUMP](0x028)M0_RST =0x0
[4240] [LK_DDP/DUMP](0x02c)M0_MOD =0x2f940
[4240] [LK_DDP/DUMP](0x030)M0_SOF =0x1
[4240] [LK_DDP/DUMP](0x040)M1_EN =0x0
[4240] [LK_DDP/DUMP](0x048)M1_RST =0x0
[4240] [LK_DDP/DUMP](0x04c)M1_MOD =0x0
[4240] [LK_DDP/DUMP](0x050)M1_SOF =0x0
[4240] [LK_DDP/DUMP](0x060)M2_EN =0x0
[4260] [LK_DDP/DUMP](0x068)M2_RST =0x0
[4260] [LK_DDP/DUMP](0x06c)M2_MOD =0x0
[4260] [LK_DDP/DUMP](0x070)M2_SOF =0x0
[4260] [LK_DDP/DUMP](0x080)M3_EN =0x0
[4260] [LK_DDP/DUMP](0x088)M3_RST =0x0
[4260] [LK_DDP/DUMP](0x08c)M3_MOD =0x0
[4260] [LK_DDP/DUMP](0x090)M3_SOF =0x0
[4260] [LK_DDP/DUMP](0x0a0)M4_EN =0x0
[4260] [LK_DDP/DUMP](0x0a8)M4_RST =0x0
[4260] [LK_DDP/DUMP](0x0ac)M4_MOD =0x0
[4260] [LK_DDP/DUMP](0x0b0)M4_SOF =0x0
[4260] [LK_DDP/DUMP](0x0c0)M5_EN =0x0
[4260] [LK_DDP/DUMP](0x0c8)M5_RST =0x0
[4260] [LK_DDP/DUMP](0x0cc)M5_MOD =0x0
[4260] [LK_DDP/DUMP](0x0d0)M5_SOF =0x0
[4260] [LK_DDP/DUMP](0x200)DEBUG_OUT_SEL =0x0
[4260] [DISP]func|disp_lcm_is_video_mode
[4260] [PROFILE] ------- disp init takes 1871 ms --------
[partition_get_index]find preloader index 0
[partition_get_index]find preloader index 0
[partition_get_index]find seccfg index 11
[partition_get_index]find secro index 13
[partition_get_index]find seccfg index 11
[partition_get_index]find seccfg index 11
[SEC_CFG] sec_read_seccfg fail:3001
[SEC_INIT] sec_func_init -- fail to search seccfg
[SBC] NS-CHIP
[SEC_CFG] initializing seccfg
[SBC] NS-CHIP
[SBC] NS-CHIP
[partition_get_index]find secro index 13
[partition_get_index]find secro index 13
[partition_get_index]find secro index 13
[partition_get_index]find secro index 13
[SEC_SRO] Search SRO - SRO Ready
[SEC_INIT] Search SECRO - SW sec boot configured (0, 0)
[SEC_INIT] Search SECRO - SDL configuration[LOCK] (1, 1, 1, 1)
[SEC_INIT] Search SECRO - SB configuration[LOCK] (1, 1, 1, 1, 1, 1, 1, 1)
[SEC_INIT] Search SECRO - SDL configuration[UNLOCK] (2, 2, 2, 2)
[SEC_INIT] Search SECRO - SB configuration[UNLOCK] (2, 2, 2, 2, 2, 2, 2, 2)
[SEC_INIT] Search SECRO - SDL configuration[VERIFIED] (1, 1, 1, 2)
[SEC_INIT] Search SECRO - SB configuration[VERIFIED] (1, 1, 1, 1, 2, 2, 2, 2)
[SEC_INIT] Search SECRO - SDL configuration[CUSTOM] (1, 1, 1, 1)
[SEC_INIT] Search SECRO - SB configuration[CUSTOM] (1, 1, 1, 1, 1, 1)
[SEC_POLICY] lock state = 0x0(default)
[SEC_POLICY] use default sec policy
[SEC_POLICY] dl_format_lock = 0x1
[SEC_POLICY] dl_1st_loader_lock = 0x1
[SEC_POLICY] dl_2nd_loader_lock = 0x1
[SEC_POLICY] dl_image_lock = 0x1
[SEC_POLICY] dl_tee_lock = 0x1
[SEC_POLICY] boot_chk_2nd_loader = 0x2
[SEC_POLICY] boot_chk_logo = 0x2
[SEC_POLICY] boot_chk_bootimg = 0x2
[SEC_POLICY] boot_chk_recovery = 0x2
[SEC_POLICY] boot_chk_system = 0x2
[SEC_POLICY] boot_chk_others = 0x2
[SEC_POLICY] boot_chk_cust1 = 0x2
[SEC_POLICY] boot_chk_cust2 = 0x2
[SEC_POLICY] boot_chk_tee = 0x2
[4340] [PROFILE] ------- Security init takes 34 ms --------
[4340] [SBC] Enter logo check
[4340] [SBC] Consume (0) ms
[4340] s_mt65xx_gd.gdfIndex=3[4340] mt_get_logo_db_addr_pa: 0x7ef30000
[4340] [PART_LK][get_part] logo
[4340] [PART_LK][get_part] logo
=========================================
[4340] [LK_BOOT] logo magic number : 0x58881688
[4340] [LK_BOOT] logo name : logo
[4340] [LK_BOOT] logo size : 2235839
=========================================
read the data of logo
[4440] [PROFILE] ------- load_logo takes 55 ms --------
kedump mini start
kedump: boot_reason(1)
RAM_CONSOLE. sram(0x10dc00) sig a0431e mismatch
RAM_CONSOLE. start: 0x43f00000, size: 0x10000
RAM_CONSOLE. lk size mismatch 0 + c0 != 100
[4460] [META] Check meta info from pre-loader: 0, 504c504c, 0
[4460] MT-RAMDUMP: No exception detected, skipped
[4460] detecting pmic just reset
[mboot_recovery_load_misc]: size is 6144
[mboot_recovery_load_misc]: misc_addr is 0x41e86020
[4460] [PART_LK][get_part] para
[4460] [LK_BOOT] Load '<null>' partition to 0x41E86020 (6144 bytes in 2 ms)
[4460] eng build
[4460] MT65XX_FACTORY_KEY 0x1
[4460] MT65XX_BOOT_MENU_KEY 0x0
[4460] MT65XX_RECOVERY_KEY 0x0
[4460] mtk detect key function key = 1
[4460] mtk detect key function key = 0
[4460] mtk detect key function key = 0
[4460] mtk detect key function key = 1
[4460] mtk detect key function key = 0
[4460] mtk detect key function key = 0
[4460] mtk detect key function key = 1
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 1
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 1
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 1
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 1
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 1
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 1
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 1
[4480] mtk detect key function key = 0
[4480] mtk detect key function key = 0
[4500] mtk detect key function key = 1
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 1
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 1
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 1
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 1
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 1
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 1
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 0
[4500] mtk detect key function key = 1
[4500] mtk detect key function key = 0
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 1
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 1
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 1
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 1
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 1
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 1
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 1
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 0
[4520] mtk detect key function key = 1
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 1
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 1
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 1
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 1
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 1
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 1
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 1
[4540] mtk detect key function key = 0
[4540] mtk detect key function key = 0
[4560] mtk detect key function key = 1
[4560] mtk detect key function key = 0
[4560] mtk detect key function key = 0
[4560] mtk detect key function key = 1
[4560] mtk detect key function key = 0
[4560] mtk detect key function key = 0
[4560] mtk detect key function key = 1
[4560] mtk detect key function key = 0
[4560] mtk detect key function key = 0
[4560] mtk detect key function key = 1
[4560] mtk detect key function key = 0
[4560] mtk detect key function key = 0
[4560] LK pmic powerkey Release
[4560] [WDT] WDT get boot reason is 1 from pre-loader
[LK_ENV]get_env off-mode-charge
[LK_ENV]set_env off-mode-charge 1
[4560] [PART_LK][get_part] para
checksum 1554
[4580] [kernel_power_off_charging_detection] off_mode_status 1
[4580] [upmu_is_chr_det] 1
< Kernel Power Off Charging Detection Ok>
[4580] [PROFILE] ------- boot mode select takes 71 ms --------
[4580] [AUXADC] ch=0 raw=26604 data=4384
[4600] [mt65xx_bat_init] check VBAT=4384 mV with 3450 mV
[4600] [Chip_Trim] Reg[0xCB8]=0x0, chip_diff_trim_value_4_0=0
[4600] [Chip_Trim] chip_diff_trim_value=1000
[4600] ******** [fgauge_initialization] reset HW FG!
[4600] [fgauge_initialization] Reg[0xcba]=0x8
[4600] [fg_get_data_ready_status] Reg[0xca4]=0x229
[4600] [fg_get_data_ready_status] Reg[0xca4]=0x629
[4600] [fgauge_read_current] : FG_CURRENT = 0
[4600] [fg_get_data_ready_status] Reg[0xca4]=0xc29
[4600] [fg_get_data_ready_status] Reg[0xca4]=0x829
[4600] [fgauge_read_current] current(discharging) = 0 mA
[4600] [fgauge_read_current] Auto adjust value due to the Rfg is 10
Ori current=0, [4600] [fgauge_read_current] new current=0
[4600] [fgauge_read_current] ori current=0
[4600] [use_chip_trim_value] 0 -> 0
[4600] [fgauge_read_current] final current=0 (ratio=86)
[4600] [fg_get_data_ready_status] Reg[0xca4]=0x229
[4620] [fg_get_data_ready_status] Reg[0xca4]=0x629
[4620] [fgauge_read_current] : FG_CURRENT = 0
[4620] [fg_get_data_ready_status] Reg[0xca4]=0xc29
[4620] [fg_get_data_ready_status] Reg[0xca4]=0x829
[4620] [fgauge_read_current] current(discharging) = 0 mA
[4620] [fgauge_read_current] Auto adjust value due to the Rfg is 10
Ori current=0, [4620] [fgauge_read_current] new current=0
[4620] [fgauge_read_current] ori current=0
[4620] [use_chip_trim_value] 0 -> 0
[4620] [fgauge_read_current] final current=0 (ratio=86)
[4620] [fg_get_data_ready_status] Reg[0xca4]=0x229
[4620] [fg_get_data_ready_status] Reg[0xca4]=0x629
[4620] [fgauge_read_current] : FG_CURRENT = 0
[4620] [fg_get_data_ready_status] Reg[0xca4]=0xc29
[4620] [fg_get_data_ready_status] Reg[0xca4]=0x829
[4620] [fgauge_read_current] current(discharging) = 0 mA
[4620] [fgauge_read_current] Auto adjust value due to the Rfg is 10
Ori current=0, [4640] [fgauge_read_current] new current=0
[4640] [fgauge_read_current] ori current=0
[4640] [use_chip_trim_value] 0 -> 0
[4640] [fgauge_read_current] final current=0 (ratio=86)
[4640] [fg_get_data_ready_status] Reg[0xca4]=0x229
[4640] [fg_get_data_ready_status] Reg[0xca4]=0x629
[4640] [fgauge_read_current] : FG_CURRENT = 0
[4640] [fg_get_data_ready_status] Reg[0xca4]=0xc29
[4640] [fg_get_data_ready_status] Reg[0xca4]=0x829
[4640] [fgauge_read_current] current(discharging) = 0 mA
[4640] [fgauge_read_current] Auto adjust value due to the Rfg is 10
Ori current=0, [4640] [fgauge_read_current] new current=0
[4640] [fgauge_read_current] ori current=0
[4640] [use_chip_trim_value] 0 -> 0
[4640] [fgauge_read_current] final current=0 (ratio=86)
[4640] [fg_get_data_ready_status] Reg[0xca4]=0x229
[4640] [fg_get_data_ready_status] Reg[0xca4]=0x629
[4640] [fgauge_read_current] : FG_CURRENT = 0
[4660] [fg_get_data_ready_status] Reg[0xca4]=0xc29
[4660] [fg_get_data_ready_status] Reg[0xca4]=0x829
[4660] [fgauge_read_current] current(discharging) = 0 mA
[4660] [fgauge_read_current] Auto adjust value due to the Rfg is 10
Ori current=0, [4660] [fgauge_read_current] new current=0
[4660] [fgauge_read_current] ori current=0
[4660] [use_chip_trim_value] 0 -> 0
[4660] [fgauge_read_current] final current=0 (ratio=86)
[4660] [fg_get_data_ready_status] Reg[0xca4]=0x229
[4660] [fg_get_data_ready_status] Reg[0xca4]=0x629
[4660] [fgauge_read_current] : FG_CURRENT = 0
[4660] [fg_get_data_ready_status] Reg[0xca4]=0xc29
[4660] [fg_get_data_ready_status] Reg[0xca4]=0x829
[4660] [fgauge_read_current] current(discharging) = 0 mA
[4660] [fgauge_read_current] Auto adjust value due to the Rfg is 10
Ori current=0, [4660] [fgauge_read_current] new current=0
[4660] [fgauge_read_current] ori current=0
[4680] [use_chip_trim_value] 0 -> 0
[4680] [fgauge_read_current] final current=0 (ratio=86)
[4680] [fg_get_data_ready_status] Reg[0xca4]=0x229
[4680] [fg_get_data_ready_status] Reg[0xca4]=0x629
[4680] [fgauge_read_current] : FG_CURRENT = 1
[4680] [fg_get_data_ready_status] Reg[0xca4]=0xc29
[4680] [fg_get_data_ready_status] Reg[0xca4]=0x829
[4680] [fgauge_read_current] current(charging) = 1 mA
[4680] [fgauge_read_current] Auto adjust value due to the Rfg is 10
Ori current=1, [4680] [fgauge_read_current] new current=2
[4680] [fgauge_read_current] ori current=2
[4680] [use_chip_trim_value] 1 -> 1
[4680] [fgauge_read_current] final current=1 (ratio=86)
[4680] ******** [fgauge_initialization] Done!
[4680] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4680] [I2C-LK] 336: I2C_ACKERR
[4680] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=1,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=2,Trans_num=1,Trans_auxlen=0,Data_size=ffff,speed=100
[4700] [I2C-LK] 209: base address 0x11009000
[4700] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=28,TRANSFER_LEN=2
[I2C-LK] TRANSAC_LEN=1,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1210
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=0
[4700] [I2C-LK] 795: Write 2 bytes fails,ret=-121.
[4700] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4700] [I2C-LK] 336: I2C_ACKERR
[4700] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=1,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=2,Trans_num=1,Trans_auxlen=0,Data_size=ffff,speed=100
[4700] [I2C-LK] 209: base address 0x11009000
[4700] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=28,TRANSFER_LEN=2
[I2C-LK] TRANSAC_LEN=1,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1210
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=0
[4720] [I2C-LK] 795: Write 2 bytes fails,ret=-121.
[4720] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4720] [I2C-LK] 336: I2C_ACKERR
[4720] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=1,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=2,Trans_num=1,Trans_auxlen=0,Data_size=ffff,speed=100
[4720] [I2C-LK] 209: base address 0x11009000
[4720] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=28,TRANSFER_LEN=2
[I2C-LK] TRANSAC_LEN=1,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1210
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=0
[4720] [I2C-LK] 795: Write 2 bytes fails,ret=-121.
[4720] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4720] [I2C-LK] 336: I2C_ACKERR
[4740] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=1,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=2,Trans_num=1,Trans_auxlen=0,Data_size=ffff,speed=100
[4740] [I2C-LK] 209: base address 0x11009000
[4740] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=28,TRANSFER_LEN=2
[I2C-LK] TRANSAC_LEN=1,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1210
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=0
[4740] [I2C-LK] 795: Write 2 bytes fails,ret=-121.
[4740] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4740] [I2C-LK] 336: I2C_ACKERR
[4740] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=1,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=2,Trans_num=1,Trans_auxlen=0,Data_size=ffff,speed=100
[4740] [I2C-LK] 209: base address 0x11009000
[4740] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=28,TRANSFER_LEN=2
[I2C-LK] TRANSAC_LEN=1,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1210
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=0
[4760] [I2C-LK] 795: Write 2 bytes fails,ret=-121.
[4760] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4760] [I2C-LK] 336: I2C_ACKERR
[4760] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=1,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=2,Trans_num=1,Trans_auxlen=0,Data_size=ffff,speed=100
[4760] [I2C-LK] 209: base address 0x11009000
[4760] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=28,TRANSFER_LEN=2
[I2C-LK] TRANSAC_LEN=1,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1210
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=0
[4760] [I2C-LK] 795: Write 2 bytes fails,ret=-121.
[4780] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4780] [I2C-LK] 336: I2C_ACKERR
[4780] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=ffff,speed=100
[4780] [I2C-LK] 209: base address 0x11009000
[4780] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1
[I2C-LK] TRANSAC_LEN=2,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1101
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=1
[4780] [I2C-LK] 835: write_read 0x10001 bytes fails,ret=-121.
[0x0]=0x0
[4780] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4780] [I2C-LK] 336: I2C_ACKERR
[4780] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=ffff,speed=100
[4800] [I2C-LK] 209: base address 0x11009000
[4800] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1
[I2C-LK] TRANSAC_LEN=2,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1101
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=1
[4800] [I2C-LK] 835: write_read 0x10001 bytes fails,ret=-121.
[0x1]=0x1
[4800] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4800] [I2C-LK] 336: I2C_ACKERR
[4800] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=ffff,speed=100
[4800] [I2C-LK] 209: base address 0x11009000
[4800] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1
[I2C-LK] TRANSAC_LEN=2,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1101
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=1
[4820] [I2C-LK] 835: write_read 0x10001 bytes fails,ret=-121.
[0x2]=0x2
[4820] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4820] [I2C-LK] 336: I2C_ACKERR
[4820] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=ffff,speed=100
[4820] [I2C-LK] 209: base address 0x11009000
[4820] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1
[I2C-LK] TRANSAC_LEN=2,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1101
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=1
[4820] [I2C-LK] 835: write_read 0x10001 bytes fails,ret=-121.
[0x3]=0x3
[4820] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4830] [I2C-LK] 336: I2C_ACKERR
[4840] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=ffff,speed=100
[4840] [I2C-LK] 209: base address 0x11009000
[4840] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1
[I2C-LK] TRANSAC_LEN=2,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1101
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=1
[4840] [I2C-LK] 835: write_read 0x10001 bytes fails,ret=-121.
[0x4]=0x4
[4840] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4840] [I2C-LK] 336: I2C_ACKERR
[4840] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=ffff,speed=100
[4840] [I2C-LK] 209: base address 0x11009000
[4860] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1
[I2C-LK] TRANSAC_LEN=2,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1101
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=1
[4860] [I2C-LK] 835: write_read 0x10001 bytes fails,ret=-121.
[0x5]=0x5
[4860] [I2C-LK] 330: id=2,addr: 6a, transfer error
[4860] [I2C-LK] 336: I2C_ACKERR
[4860] [I2C-LK] 206: I2C structure:
[I2C-LK] Clk=13600,Id=2,Mode=1,St_rs=0,Dma_en=0,Op=3,Poll_en=1,Irq_stat=2
[I2C-LK] Trans_len=1,Trans_num=2,Trans_auxlen=1,Data_size=ffff,speed=100
[4860] [I2C-LK] 209: base address 0x11009000
[4860] [I2C-LK] 229: I2C register:
[I2C-LK] SLAVE_ADDR=d4,INTR_MASK=f8,INTR_STAT=3,CONTROL=38,TRANSFER_LEN=1
[I2C-LK] TRANSAC_LEN=2,DELAY_LEN=2,TIMING=1121,START=0,FIFO_STAT=1101
[I2C-LK] IO_CONFIG=3,HS=102,DCM_EN=0,DEBUGSTAT=40,EXT_CONF=8001,TRANSFER_LEN_AUX=1
[4880] [I2C-LK] 835: write_read 0x10001 bytes fails,ret=-121.
[0x6]=0x6
[5000] [fgauge_read_IM_current] : FG_CURRENT = 0
[5000] [fgauge_read_IM_current] current(discharging) = 0 mA
[5000] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [5020] [fgauge_read_IM_current] new current=0
[5020] [fgauge_read_IM_current] ori current=0
[5020] [use_chip_trim_value] 0 -> 0
[5020] [fgauge_read_IM_current] final current=0 (ratio=86)
[5020] [1,Trigger ADC PTIM mode] volt1=43814, curr_1=0
[5020] [2,enable dummy load][5160] [fgauge_read_IM_current] : FG_CURRENT = ffff
[5160] [fgauge_read_IM_current] current(discharging) = 0 mA
[5160] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [5160] [fgauge_read_IM_current] new current=0
[5160] [fgauge_read_IM_current] ori current=0
[5160] [use_chip_trim_value] 0 -> 0
[5160] [fgauge_read_IM_current] final current=0 (ratio=86)
[5160] [3,Trigger ADC PTIM mode again] volt2=43825, curr_2=0
[5160] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[5160] [5,Calculate Rac] volt_1=43814,volt_2=43825,curr_1=0,curr_2=0,rac_cal=0,ret=-1,retry_count=0
[5160] [6,Calculate Rac] 43814,43825,0,0,0,-1,0
[5200] [fgauge_read_IM_current] : FG_CURRENT = 1
[5200] [fgauge_read_IM_current] current(charging) = 1 mA
[5200] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [5200] [fgauge_read_IM_current] new current=2
[5200] [fgauge_read_IM_current] ori current=2
[5200] [use_chip_trim_value] 1 -> 1
[5210] [fgauge_read_IM_current] final current=1 (ratio=86)
[5220] [1,Trigger ADC PTIM mode] volt1=43800, curr_1=1
[5220] [2,enable dummy load][5340] [fgauge_read_IM_current] : FG_CURRENT = 0
[5340] [fgauge_read_IM_current] current(discharging) = 0 mA
[5360] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [5360] [fgauge_read_IM_current] new current=0
[5360] [fgauge_read_IM_current] ori current=0
[5360] [use_chip_trim_value] 0 -> 0
[5360] [fgauge_read_IM_current] final current=0 (ratio=86)
[5360] [3,Trigger ADC PTIM mode again] volt2=43818, curr_2=0
[5360] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[5360] [5,Calculate Rac] volt_1=43800,volt_2=43818,curr_1=1,curr_2=0,rac_cal=0,ret=-1,retry_count=1
[5360] [6,Calculate Rac] 43800,43818,1,0,0,-1,1
[5400] [fgauge_read_IM_current] : FG_CURRENT = 1
[5400] [fgauge_read_IM_current] current(charging) = 1 mA
[5400] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [5400] [fgauge_read_IM_current] new current=2
[5400] [fgauge_read_IM_current] ori current=2
[5400] [use_chip_trim_value] 1 -> 1
[5400] [fgauge_read_IM_current] final current=1 (ratio=86)
[5400] [1,Trigger ADC PTIM mode] volt1=43828, curr_1=1
[5400] [2,enable dummy load][5540] [fgauge_read_IM_current] : FG_CURRENT = 0
[5540] [fgauge_read_IM_current] current(discharging) = 0 mA
[5540] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [5540] [fgauge_read_IM_current] new current=0
[5540] [fgauge_read_IM_current] ori current=0
[5560] [use_chip_trim_value] 0 -> 0
[5560] [fgauge_read_IM_current] final current=0 (ratio=86)
[5560] [3,Trigger ADC PTIM mode again] volt2=43820, curr_2=0
[5560] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[5560] [5,Calculate Rac] volt_1=43828,volt_2=43820,curr_1=1,curr_2=0,rac_cal=0,ret=-1,retry_count=2
[5560] [6,Calculate Rac] 43828,43820,1,0,0,-1,2
[5600] [fgauge_read_IM_current] : FG_CURRENT = 1
[5600] [fgauge_read_IM_current] current(charging) = 1 mA
[5600] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [5600] [fgauge_read_IM_current] new current=2
[5600] [fgauge_read_IM_current] ori current=2
[5600] [use_chip_trim_value] 1 -> 1
[5600] [fgauge_read_IM_current] final current=1 (ratio=86)
[5600] [1,Trigger ADC PTIM mode] volt1=43814, curr_1=1
[5600] [2,enable dummy load][5740] [fgauge_read_IM_current] : FG_CURRENT = ffff
[5740] [fgauge_read_IM_current] current(discharging) = 0 mA
[5740] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [5740] [fgauge_read_IM_current] new current=0
[5740] [fgauge_read_IM_current] ori current=0
[5740] [use_chip_trim_value] 0 -> 0
[5740] [fgauge_read_IM_current] final current=0 (ratio=86)
[5740] [3,Trigger ADC PTIM mode again] volt2=43828, curr_2=0
[5760] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[5760] [5,Calculate Rac] volt_1=43814,volt_2=43828,curr_1=1,curr_2=0,rac_cal=0,ret=-1,retry_count=0
[5760] [6,Calculate Rac] 43814,43828,1,0,0,-1,0
[5800] [fgauge_read_IM_current] : FG_CURRENT = 1
[5800] [fgauge_read_IM_current] current(charging) = 1 mA
[5800] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [5800] [fgauge_read_IM_current] new current=2
[5800] [fgauge_read_IM_current] ori current=2
[5800] [use_chip_trim_value] 1 -> 1
[5800] [fgauge_read_IM_current] final current=1 (ratio=86)
[5800] [1,Trigger ADC PTIM mode] volt1=43802, curr_1=1
[5800] [2,enable dummy load][5940] [fgauge_read_IM_current] : FG_CURRENT = 4
[5940] [fgauge_read_IM_current] current(charging) = 6 mA
[5940] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=6, [5940] [fgauge_read_IM_current] new current=12
[5940] [fgauge_read_IM_current] ori current=12
[5940] [use_chip_trim_value] 10 -> 10
[5940] [fgauge_read_IM_current] final current=10 (ratio=86)
[5940] [3,Trigger ADC PTIM mode again] volt2=43848, curr_2=10
[5940] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[5940] [5,Calculate Rac] volt_1=43802,volt_2=43848,curr_1=1,curr_2=10,rac_cal=0,ret=-1,retry_count=1
[5940] [6,Calculate Rac] 43802,43848,1,10,0,-1,1
[5980] [fgauge_read_IM_current] : FG_CURRENT = 1
[5980] [fgauge_read_IM_current] current(charging) = 1 mA
[5980] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [6000] [fgauge_read_IM_current] new current=2
[6000] [fgauge_read_IM_current] ori current=2
[6000] [use_chip_trim_value] 1 -> 1
[6000] [fgauge_read_IM_current] final current=1 (ratio=86)
[6000] [1,Trigger ADC PTIM mode] volt1=43828, curr_1=1
[6000] [2,enable dummy load][6140] [fgauge_read_IM_current] : FG_CURRENT = 1
[6140] [fgauge_read_IM_current] current(charging) = 1 mA
[6140] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [6140] [fgauge_read_IM_current] new current=2
[6140] [fgauge_read_IM_current] ori current=2
[6140] [use_chip_trim_value] 1 -> 1
[6140] [fgauge_read_IM_current] final current=1 (ratio=86)
[6140] [3,Trigger ADC PTIM mode again] volt2=43827, curr_2=1
[6140] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[6140] [5,Calculate Rac] volt_1=43828,volt_2=43827,curr_1=1,curr_2=1,rac_cal=0,ret=-1,retry_count=2
[6140] [6,Calculate Rac] 43828,43827,1,1,0,-1,2
[6180] [fgauge_read_IM_current] : FG_CURRENT = 1
[6180] [fgauge_read_IM_current] current(charging) = 1 mA
[6180] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [6180] [fgauge_read_IM_current] new current=2
[6180] [fgauge_read_IM_current] ori current=2
[6180] [use_chip_trim_value] 1 -> 1
[6200] [fgauge_read_IM_current] final current=1 (ratio=86)
[6200] [1,Trigger ADC PTIM mode] volt1=43812, curr_1=1
[6200] [2,enable dummy load][6320] [fgauge_read_IM_current] : FG_CURRENT = 2
[6320] [fgauge_read_IM_current] current(charging) = 3 mA
[6340] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=3, [6340] [fgauge_read_IM_current] new current=6
[6340] [fgauge_read_IM_current] ori current=6
[6340] [use_chip_trim_value] 5 -> 5
[6340] [fgauge_read_IM_current] final current=5 (ratio=86)
[6340] [3,Trigger ADC PTIM mode again] volt2=43823, curr_2=5
[6340] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[6340] [5,Calculate Rac] volt_1=43812,volt_2=43823,curr_1=1,curr_2=5,rac_cal=0,ret=-1,retry_count=0
[6340] [6,Calculate Rac] 43812,43823,1,5,0,-1,0
[6380] [fgauge_read_IM_current] : FG_CURRENT = 0
[6380] [fgauge_read_IM_current] current(discharging) = 0 mA
[6380] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [6380] [fgauge_read_IM_current] new current=0
[6380] [fgauge_read_IM_current] ori current=0
[6380] [use_chip_trim_value] 0 -> 0
[6380] [fgauge_read_IM_current] final current=0 (ratio=86)
[6380] [1,Trigger ADC PTIM mode] volt1=43822, curr_1=0
[6380] [2,enable dummy load][6520] [fgauge_read_IM_current] : FG_CURRENT = 1
[6520] [fgauge_read_IM_current] current(charging) = 1 mA
[6520] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [6520] [fgauge_read_IM_current] new current=2
[6530] [fgauge_read_IM_current] ori current=2
[6540] [use_chip_trim_value] 1 -> 1
[6540] [fgauge_read_IM_current] final current=1 (ratio=86)
[6540] [3,Trigger ADC PTIM mode again] volt2=43805, curr_2=1
[6540] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[6540] [5,Calculate Rac] volt_1=43822,volt_2=43805,curr_1=0,curr_2=1,rac_cal=0,ret=-1,retry_count=1
[6540] [6,Calculate Rac] 43822,43805,0,1,0,-1,1
[6580] [fgauge_read_IM_current] : FG_CURRENT = ffff
[6580] [fgauge_read_IM_current] current(discharging) = 0 mA
[6580] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [6580] [fgauge_read_IM_current] new current=0
[6580] [fgauge_read_IM_current] ori current=0
[6580] [use_chip_trim_value] 0 -> 0
[6580] [fgauge_read_IM_current] final current=0 (ratio=86)
[6580] [1,Trigger ADC PTIM mode] volt1=43827, curr_1=0
[6580] [2,enable dummy load][6720] [fgauge_read_IM_current] : FG_CURRENT = fffc
[6720] [fgauge_read_IM_current] current(discharging) = 4 mA
[6720] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=4, [6720] [fgauge_read_IM_current] new current=8
[6720] [fgauge_read_IM_current] ori current=8
[6720] [use_chip_trim_value] 6 -> 6
[6720] [fgauge_read_IM_current] final current=6 (ratio=86)
[6720] [3,Trigger ADC PTIM mode again] volt2=43815, curr_2=6
[6740] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[6740] [5,Calculate Rac] volt_1=43827,volt_2=43815,curr_1=0,curr_2=6,rac_cal=0,ret=-1,retry_count=2
[6740] [6,Calculate Rac] 43827,43815,0,6,0,-1,2
[6780] [fgauge_read_IM_current] : FG_CURRENT = ffff
[6780] [fgauge_read_IM_current] current(discharging) = 0 mA
[6780] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [6780] [fgauge_read_IM_current] new current=0
[6780] [fgauge_read_IM_current] ori current=0
[6780] [use_chip_trim_value] 0 -> 0
[6780] [fgauge_read_IM_current] final current=0 (ratio=86)
[6780] [1,Trigger ADC PTIM mode] volt1=43832, curr_1=0
[6780] [2,enable dummy load][6920] [fgauge_read_IM_current] : FG_CURRENT = ffff
[6920] [fgauge_read_IM_current] current(discharging) = 0 mA
[6920] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [6920] [fgauge_read_IM_current] new current=0
[6920] [fgauge_read_IM_current] ori current=0
[6920] [use_chip_trim_value] 0 -> 0
[6920] [fgauge_read_IM_current] final current=0 (ratio=86)
[6920] [3,Trigger ADC PTIM mode again] volt2=43807, curr_2=0
[6920] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[6920] [5,Calculate Rac] volt_1=43832,volt_2=43807,curr_1=0,curr_2=0,rac_cal=0,ret=-1,retry_count=0
[6940] [6,Calculate Rac] 43832,43807,0,0,0,-1,0
[6960] [fgauge_read_IM_current] : FG_CURRENT = ffff
[6960] [fgauge_read_IM_current] current(discharging) = 0 mA
[6980] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [6980] [fgauge_read_IM_current] new current=0
[6980] [fgauge_read_IM_current] ori current=0
[6980] [use_chip_trim_value] 0 -> 0
[6980] [fgauge_read_IM_current] final current=0 (ratio=86)
[6980] [1,Trigger ADC PTIM mode] volt1=43825, curr_1=0
[6980] [2,enable dummy load][7120] [fgauge_read_IM_current] : FG_CURRENT = ffff
[7120] [fgauge_read_IM_current] current(discharging) = 0 mA
[7120] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [7120] [fgauge_read_IM_current] new current=0
[7120] [fgauge_read_IM_current] ori current=0
[7120] [use_chip_trim_value] 0 -> 0
[7120] [fgauge_read_IM_current] final current=0 (ratio=86)
[7120] [3,Trigger ADC PTIM mode again] volt2=43800, curr_2=0
[7120] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[7120] [5,Calculate Rac] volt_1=43825,volt_2=43800,curr_1=0,curr_2=0,rac_cal=0,ret=-1,retry_count=1
[7120] [6,Calculate Rac] 43825,43800,0,0,0,-1,1
[7160] [fgauge_read_IM_current] : FG_CURRENT = ffff
[7160] [fgauge_read_IM_current] current(discharging) = 0 mA
[7160] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [7160] [fgauge_read_IM_current] new current=0
[7160] [fgauge_read_IM_current] ori current=0
[7180] [use_chip_trim_value] 0 -> 0
[7180] [fgauge_read_IM_current] final current=0 (ratio=86)
[7180] [1,Trigger ADC PTIM mode] volt1=43842, curr_1=0
[7180] [2,enable dummy load][7300] [fgauge_read_IM_current] : FG_CURRENT = fffc
[7320] [fgauge_read_IM_current] current(discharging) = 4 mA
[7320] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=4, [7320] [fgauge_read_IM_current] new current=8
[7320] [fgauge_read_IM_current] ori current=8
[7320] [use_chip_trim_value] 6 -> 6
[7320] [fgauge_read_IM_current] final current=6 (ratio=86)
[7320] [3,Trigger ADC PTIM mode again] volt2=43810, curr_2=6
[7320] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[7320] [5,Calculate Rac] volt_1=43842,volt_2=43810,curr_1=0,curr_2=6,rac_cal=0,ret=-1,retry_count=2
[7320] [6,Calculate Rac] 43842,43810,0,6,0,-1,2
[7360] [fgauge_read_IM_current] : FG_CURRENT = fffe
[7360] [fgauge_read_IM_current] current(discharging) = 1 mA
[7360] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [7360] [fgauge_read_IM_current] new current=2
[7360] [fgauge_read_IM_current] ori current=2
[7360] [use_chip_trim_value] 1 -> 1
[7360] [fgauge_read_IM_current] final current=1 (ratio=86)
[7360] [1,Trigger ADC PTIM mode] volt1=43812, curr_1=1
[7370] [2,enable dummy load][7500] [fgauge_read_IM_current] : FG_CURRENT = fffe
[7500] [fgauge_read_IM_current] current(discharging) = 1 mA
[7500] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=1, [7510] [fgauge_read_IM_current] new current=2
[7520] [fgauge_read_IM_current] ori current=2
[7520] [use_chip_trim_value] 1 -> 1
[7520] [fgauge_read_IM_current] final current=1 (ratio=86)
[7520] [3,Trigger ADC PTIM mode again] volt2=43794, curr_2=1
[7520] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[7520] [5,Calculate Rac] volt_1=43812,volt_2=43794,curr_1=1,curr_2=1,rac_cal=0,ret=-1,retry_count=0
[7520] [6,Calculate Rac] 43812,43794,1,1,0,-1,0
[7560] [fgauge_read_IM_current] : FG_CURRENT = fffd
[7560] [fgauge_read_IM_current] current(discharging) = 3 mA
[7560] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=3, [7560] [fgauge_read_IM_current] new current=6
[7560] [fgauge_read_IM_current] ori current=6
[7560] [use_chip_trim_value] 5 -> 5
[7560] [fgauge_read_IM_current] final current=5 (ratio=86)
[7560] [1,Trigger ADC PTIM mode] volt1=43832, curr_1=5
[7560] [2,enable dummy load][7700] [fgauge_read_IM_current] : FG_CURRENT = ffff
[7700] [fgauge_read_IM_current] current(discharging) = 0 mA
[7700] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [7700] [fgauge_read_IM_current] new current=0
[7700] [fgauge_read_IM_current] ori current=0
[7700] [use_chip_trim_value] 0 -> 0
[7700] [fgauge_read_IM_current] final current=0 (ratio=86)
[7720] [3,Trigger ADC PTIM mode again] volt2=43818, curr_2=0
[7720] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[7720] [5,Calculate Rac] volt_1=43832,volt_2=43818,curr_1=5,curr_2=0,rac_cal=0,ret=-1,retry_count=1
[7720] [6,Calculate Rac] 43832,43818,5,0,0,-1,1
[7760] [fgauge_read_IM_current] : FG_CURRENT = fffd
[7760] [fgauge_read_IM_current] current(discharging) = 3 mA
[7760] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=3, [7760] [fgauge_read_IM_current] new current=6
[7760] [fgauge_read_IM_current] ori current=6
[7760] [use_chip_trim_value] 5 -> 5
[7760] [fgauge_read_IM_current] final current=5 (ratio=86)
[7760] [1,Trigger ADC PTIM mode] volt1=43817, curr_1=5
[7760] [2,enable dummy load][7900] [fgauge_read_IM_current] : FG_CURRENT = 0
[7900] [fgauge_read_IM_current] current(discharging) = 0 mA
[7900] [fgauge_read_IM_current] Auto adjust value due to the Rfg is 10
Ori current=0, [7900] [fgauge_read_IM_current] new current=0
[7900] [fgauge_read_IM_current] ori current=0
[7900] [use_chip_trim_value] 0 -> 0
[7900] [fgauge_read_IM_current] final current=0 (ratio=86)
[7900] [3,Trigger ADC PTIM mode again] volt2=43830, curr_2=0
[7900] [4,Calculate Rac] bypass due to (curr_x-curr_y) < 40mA
[7900] [5,Calculate Rac] volt_1=43817,volt_2=43830,curr_1=5,curr_2=0,rac_cal=0,ret=-1,retry_count=2
[7920] [6,Calculate Rac] 43817,43830,5,0,0,-1,2
[7920] [dlpt_R] -1,-1,-1,-1,-1 [1000:0:0]170
[7920] [AUXADC] ch=0 raw=26602 data=4383
[7920] [check_bat_protect_status]: check VBAT=4383 mV with 3450 mV, start charging...
[7920] [check_bat_protect_status]: check VBAT=4383 mV with 3450 mV, stop charging...
[7920] [PROFILE] ------- battery init takes 1694 ms --------
[7920] [PROFILE] ------- RTC boot check Init takes 0 ms --------
[7920] [lk logo: mt_disp_show_boot_logo 143]
[7920] [lk logo: init_fb_screen 67]
[7920] mt_get_logo_db_addr: 0x7ef30000
[7920] [lk logo: init_fb_screen 85]MTK_LCM_PHYSICAL_ROTATION = 0
[7920] [lk logo: sync_anim_version 50]
[7920] [lk logo: init_fb_screen 108]pinfo[0]=0x00000033, pinfo[1]=0x00221dbf, pinfo[2]=212
[7940] [lk logo: init_fb_screen 110]define ANIMATION_NEW:show new animation with capacity num
[7940] [lk logo: init_fb_screen 111]CAPACITY_LEFT =278, CAPACITY_TOP =556
[7940] [lk logo: init_fb_screen 112]LCM_HEIGHT=441, LCM_WIDTH=817
[LK_ENV]get_env changelogo
[LK_ENV]get_env changelogo
[LK_ENV]get_env changelogo
[LK_ENV]get_env changelogo
[LK_ENV]get_env changelogo
[LK_ENV]get_env changelogo
[LK_ENV]get_env changelogo
[7940] mt_get_tempfb_addr: 0x7fa60000
[7940] [show_animation_common: check_logo_index_valid 71]logonum =51, index =0
[7940] show_animation_common, in_addr=0x7ef300d4, logolen=12214
[7940] [decompress_logo decompress_logo 48]in=0x7ef300d4, out=0x7fa60000, inlen=12214, logolen=3768320
[7990] [decompress_logo decompress_logo 97]have=3686400
[8000] [show_animation_common: fill_animation_logo 124]bits = 32
[8000] [show_logo_common: fill_rect_with_content 427]
[8000] [show_logo_common: fill_rect_with_content_by_32bit_argb8888 128]
[8000] [show_logo_common]dst_addr= 0xff000000, color_addr= 0xff000000, i= 0, j=0
[8000] [show_logo_common]dst_addr= 0xff000000, color_addr= 0xff000000, i= 0, j=719
[8140] [show_logo_common]dst_addr= 0xff000000, color_addr= 0xff000000, i= 1279, j=0
[8160] [show_logo_common]dst_addr= 0xff000000, color_addr= 0xff000000, i= 1279, j=719
[8160] fb dump: 0xff000000, 0xff000000, 0xff000000, 0xff000000
[8160] [DISP]func|primary_display_trigger
[8160] [LK_DDP/ddp_manager]path check busy on scenario primary_disp
[8160] [DISP]func|ddp_dsi_is_busy
[8160] [LK_DDP/ddp_manager]dsi0 is busy
[8160] [DISP]func|disp_lcm_is_video_mode
[8160] [DISP]func|disp_lcm_is_video_mode
[8160] [LEDS]LK: mt65xx_backlight_on:level = 255
[8160] [LEDS]LK: lcd-backlight level is 255
[8160] [LK_DDP/PWM][PWM] disp_pwm_set_backlight(id = 0x1, level_1024 = 1023)
[8160] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000000
[8160] [LK_DDP/PWM][PWM] set reg[0x1100e014] = 0x03ff03ff
[8160] [LK_DDP/PWM][PWM] set reg[0x1100e000] = 0x00000001
[8170] [LK_DDP/PWM][PWM] disp_pwm_set_enabled: PWN_EN = 0x1
[8180] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000001
[8180] [LK_DDP/PWM][PWM] set reg[0x1100e008] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e000] = 0x00000001
[8180] [LK_DDP/PWM][PWM] reg[0x1100e004] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e008] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e00c] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e010] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e014] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e018] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e01c] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e020] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e024] = 0x00000000
[8180] [LK_DDP/PWM][PWM] reg[0x1100e028] = 0x00000000
[8180] fb dump: 0xff000000, 0xff000000, 0xff000000, 0xff000000
[8200] [DISP]func|primary_display_trigger
[8200] [LK_DDP/ddp_manager]path check busy on scenario primary_disp
[8200] [DISP]func|ddp_dsi_is_busy
[8200] [LK_DDP/ddp_manager]dsi0 is busy
[8200] [DISP]func|disp_lcm_is_video_mode
[8200] [DISP]func|disp_lcm_is_video_mode
[8200] [PROFILE] ------- backlight takes 17 ms --------
[8200] [PROFILE] ------- show logo takes 140 ms --------
[LK_ENV]get_env hibboot
[8220] fb dump: 0xff000000, 0xff000000, 0xff000000, 0xff000000
[8220] [DISP]func|primary_display_trigger
[8220] [LK_DDP/ddp_manager]path check busy on scenario primary_disp
[8220] [DISP]func|ddp_dsi_is_busy
[8220] [LK_DDP/ddp_manager]dsi0 is busy
[8220] [DISP]func|disp_lcm_is_video_mode
[8220] [DISP]func|disp_lcm_is_video_mode
[8220] [PROFILE] ------- sw_env takes 14 ms --------
[8220] [PROFILE] ------- platform_init takes 4176 ms --------
[8240] initializing target
[8240] calling apps_init()
[SEC_POLICY] lock state = 0x0(default)
[SEC_POLICY] security policy backup (0)[SBC] Consume (0) ms
[SBC] Consume (0) ms
[SBC] Consume (0) ms
[SBC] Total Consume (2) ms
[SEC_POLICY] use default sec policy
[SEC_POLICY] dl_format_lock = 0x1
[SEC_POLICY] dl_1st_loader_lock = 0x1
[SEC_POLICY] dl_2nd_loader_lock = 0x1
[SEC_POLICY] dl_image_lock = 0x1
[SEC_POLICY] dl_tee_lock = 0x1
[SEC_POLICY] boot_chk_2nd_loader = 0x2
[SEC_POLICY] boot_chk_logo = 0x2
[SEC_POLICY] boot_chk_bootimg = 0x2
[SEC_POLICY] boot_chk_recovery = 0x2
[SEC_POLICY] boot_chk_system = 0x2
[SEC_POLICY] boot_chk_others = 0x2
[SEC_POLICY] boot_chk_cust1 = 0x2
[SEC_POLICY] boot_chk_cust2 = 0x2
[SEC_POLICY] boot_chk_tee = 0x2
[SEC_POLICY] security policy restore (0)[8240] [PART_LK][get_part] boot
[8240] [PART_LK][get_part] boot
[8240] part page addr is 0x1d80000
============================================================
[8260] [LK_BOOT] Android Partition Name : boot
[8260] [LK_BOOT] Android Boot IMG Hdr - Magic : ANDROID
[8260] [LK_BOOT] Android Boot IMG Hdr - Kernel Size : 0x006EA8E2
[8260] [LK_BOOT] Android Boot IMG Hdr - Kernel Address : 0x40008000
[8260] [LK_BOOT] Android Boot IMG Hdr - Rootfs Size : 0x0012A31C
[8260] [LK_BOOT] Android Boot IMG Hdr - Rootfs Address : 0x44000000
[8260] [LK_BOOT] Android Boot IMG Hdr - Tags Address : 0x4E000000
[8260] [LK_BOOT] Android Boot IMG Hdr - Page Size : 0x00000800
[8260] [LK_BOOT] Android Boot IMG Hdr - Command Line : bootopt=64S3,32N2,32N2
============================================================
> page count of kernel image = 3542
> kernel mem offset = 0x40008000
> rootfs mem offset = 0x406f3000
> boot image size = 0x816000
[8280] [PART_LK][get_part] boot
check mkimg header
[8280] [LK_BOOT] KERNEL partition magic not match
no mkimg header in kernel image
read the data of boot (size = 0x816000)
> from - 0x0000000001d80800 (skip boot img hdr)
> to - 0x40008000 (starts with kernel img hdr)
[8640] [LK_BOOT] ROOTFS partition magic not match
no mkimg header in ramdisk image
[8640] [PROFILE] ------- load boot.img takes 203 ms --------
[8640] [DISP]func|disp_lcm_get_name
[8640] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9999
[8680] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9895
[8700] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9845
[8740] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9844
[8740] mt_disp_get_lcd_time, fps=6124
[8740] 32 bits kernel
[8740] dtb_addr = 0x406E2DB8, dtb_size = 0x0000FB2A
[8740] [PTP][LK] first_volt = 0x58
[8740] [PTP][LK] second_volt = 0x58
[8740] [PTP][LK] third_volt = 0x48
[8740] [PTP][LK] have_550 = 0x1
[8740] model=MT6737
[8740] mblock[0].start: 0x40000000, size: 0x3f330000
[8740] mem_reg_property[0].start_hi = 0x00000000
[8740] mem_reg_property[0].start_lo = 0x00000040
[8740] mem_reg_property[0].size_hi = 0x00000000
[8740] mem_reg_property[0].size_lo = 0x0000333F
[8740] j:0, mblock[0].rank: 0, size: 0x3f330000
[8760] rsv mem rsv_mem_reg_property[0].start_hi = 0x00000000
[8760] rsv mem rsv_mem_reg_property[0].start_lo = 0x00000040
[8760] rsv mem rsv_mem_reg_property[0].size_hi = 0x00000000
[8760] rsv mem rsv_mem_reg_property[0].size_lo = 0x0000333F
[8760] target_atag_imix_r:170
[8760] Not Support VCORE DVFS
[8760] SSSS:0x0
[8760] SSSS:0x0
[8760] SSSS:0x4
[8760] SSSS:0x28900010
[8760] SSSS:0x335
[8760] SSSS:0x0
[8770] [DISP]func|disp_lcm_get_name
[8780] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9999
[8800] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9857
[8840] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9845
[8860] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9844
[8860] mt_disp_get_lcd_time, fps=6124
[8860] videolfb - fb_base = 0x7f330000
[8860] videolfb - islcmfound = 1
[8900] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9857
[8920] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9844
[8960] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9844
[9000] [LK_DDP/RDMA] RDMA0 polling interrupt ret =9844
[9000] mt_disp_get_lcd_time, fps=6105
[9000] videolfb - fps = 6105
[9000] videolfb - vram = 13172736
[9000] videolfb - lcmname = ili9881c_hd720_dsi_vdo_cpt
[9000] Create PTP DT OK
start dump lk masp atag
dump sw sbc:22, sw sdl:22 , hw sbc: 0
dump lock_state, 1
dump rid, 2ab89797, 1774b724, 3f661d23, 3478a829
[9000] create masp atag OK
[9000] tee_reserved_mem not supported
[9000] non_secure_sram not supported
[9000] [PROFILE] ------- boot_time takes 4599 ms --------
[LK_ENV]get_env hibboot
[LK_ENV]get_env resume
[9020] resume = NULL
[9020] booting linux @ 0x40008000, ramdisk @ 0x44000000 (1221404)
[9020] [LEDS]LK: leds_deinit: LEDS off
[9020] [LEDS]LK: red level is 0
[9020] [LEDS]LK: green level is 0
[9020] [LEDS]LK: blue level is 0
[9020] DRAM Rank :1
[9020] DRAM Rank[0] Start = 0x40000000, Size = 0x3ffc0000
[9020] cmdline: console=tty0 console=ttyMT1,921600n1 root=/dev/ram vmalloc=496M androidboot.hardware=mt6735 slub_max_order=0 slub_debug=O mrdump.lk=MRDUMP04 bootopt=64S3,32N2,32N2 lcm=0-ili9881c_hd720_dsi_vdo_cpt fps=6124 vram=13172736 androidboot.selinux=permis[9020] lk boot time = 4599 ms
[9020] lk boot mode = 0
[9020] lk boot reason = usb
[9020] lk finished --> jump to linux kernel 32Bit
[ 0.000000] <0>-(0)[0:swapper][name:setup&]Booting Linux on physical CPU 0x0
[ 0.000000] <0>-(0)[0:swapper]Initializing cgroup subsys cpu
[ 0.000000] <0>-(0)[0:swapper]Initializing cgroup subsys cpuacct
[ 0.000000] <0>-(0)[0:swapper][name:main&]Linux version 3.18.19 (ubuntu@ubuntu) (gcc version 4.8 (GCC) ) #5 SMP PREEMPT Mon May 16 00:35:47 CST 2022
[ 0.000000] <0>-(0)[0:swapper][name:setup&]CPU: ARMv7 Processor [410fd034] revision 4 (ARMv7), cr=10c0383d
[ 0.000000] <0>-(0)[0:swapper][name:setup&]CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
[ 0.000000] <0>-(0)[0:swapper][name:fdt&]Machine model: MT6737
[ 0.000000] <0>-(0)[0:swapper][name:fdt&][PHY layout]atf-reserved-memory@43000000 : 0x43000000 - 0x4302ffff (0x30000)
[ 0.000000] <0>-(0)[0:swapper][name:of_reserved_mem&]Reserved memory: initialized node reserve-memory-dram_r0_dummy_read, compatible id reserve-memory-dram_r0_dummy_read
[ 0.000000] <0>-(0)[0:swapper][name:of_reserved_mem&][PHY layout]reserve-memory-ccci_md1 : 0x5c000000 - 0x5f80ffff (0x3810000)
[ 0.000000] <0>-(0)[0:swapper][name:of_reserved_mem&]Reserved memory: initialized node reserve-memory-ccci_md1, compatible id mediatek,reserve-memory-ccci_md1
[ 0.000000] <0>-(0)[0:swapper][name:of_reserved_mem&][PHY layout]consys-reserve-memory : 0x5fe00000 - 0x5fefffff (0x100000)
[ 0.000000] <0>-(0)[0:swapper][name:mtk_wcn_consys_hw&][WMT-CONSYS-HW][W]reserve_memory_consys_fn: name: consys-reserve-memory, base: 0x5fe00000, size: 0x100000
[ 0.000000] <0>-(0)[0:swapper][name:of_reserved_mem&]Reserved memory: initialized node consys-reserve-memory, compatible id mediatek,consys-reserve-memory
[ 0.000000] <0>-(0)[0:swapper][name:mtk_ram_console&][memblock]ram_console-reserve-memory: 0x43f00000 - 0x43f10000 (0x10000)
[ 0.000000] <0>-(0)[0:swapper][name:of_reserved_mem&]Reserved memory: initialized node ram_console-reserved-memory@43f00000, compatible id mediatek,ram_console
[ 0.000000] <0>-(0)[0:swapper][name:mmu&]Memory policy: Data cache writealloc
[ 0.000000] <0>-(0)[0:swapper][name:mmu&][PHY layout]kernel : 0x40000000 - 0x42ffffff (0x03000000)
[ 0.000000] <0>-(0)[0:swapper][name:mmu&][PHY layout]kernel : 0x43030000 - 0x5bffffff (0x18fd0000)
[ 0.000000] <0>-(0)[0:swapper][name:mmu&][PHY layout]kernel : 0x5f810000 - 0x5fdfffff (0x005f0000)
[ 0.000000] <0>-(0)[0:swapper][name:mmu&][PHY layout]kernel : 0x5ff00000 - 0x7f32ffff (0x1f430000)
[ 0.000000] <0>-(0)[0:swapper][name:psci&]psci: probing for conduit method from DT.
[ 0.000000] <0>-(0)[0:swapper][name:psci&]psci: Using PSCI v0.1 Function IDs from DT
[ 0.000000] <0>-(0)[0:swapper][name:percpu&]PERCPU: Embedded 10 pages/cpu @dff90000 s20032 r0 d20928 u40960
[ 0.000000] <0>-(0)[0:swapper]Built 1 zonelists in Zone order, mobility grouping on. Total pages: 243184
[ 0.000000] <0>-(0)[0:swapper][name:cpu&][cpu_ntf] <00>c011eee0 (page_alloc_cpu_notify)
[ 0.000000] <0>-(0)[0:swapper][name:main&]Kernel command line: console=tty0 console=ttyMT1,921600n1 root=/dev/ram vmalloc=496M androidboot.hardware=mt6735 slub_max_order=0 slub_debug=O mrdump.lk=MRDUMP04 bootopt=64S3,32N2,32N2 lcm=0-ili9881c_hd720_dsi_vdo_cpt fps=6124 vram=13172736 androidboot.selinux=permissive printk.disable_uart=0 ddebug_query="file *mediatek* +p ; file *gpu* =_" bootprof.pl_t=8540 bootprof.lk_t=4599 boot_reason=1 androidboot.serialno=0123456789ABCDEF androidboot.bootreason=usb gpt=1 initcall_debug=1
[ 0.000000] <0>-(0)[0:swapper]PID hash table entries: 2048 (order: 1, 8192 bytes)
[ 0.000000] <0>-(0)[0:swapper]Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] <0>-(0)[0:swapper]Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] <0>-(0)[0:swapper]Memory: 939936K/976832K available (10291K kernel code, 1506K rwdata, 4432K rodata, 748K init, 9119K bss, 36896K reserved, 511164K highmem)
[ 0.000000] <0>-(0)[0:swapper]Virtual kernel memory layout:
[ 0.000000] <0> vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] <0> fixmap : 0xffc00000 - 0xffe00000 (2048 kB)
[ 0.000000] <0> vmalloc : 0xe0800000 - 0xff000000 ( 488 MB)
[ 0.000000] <0> lowmem : 0xc0000000 - 0xe0000000 ( 512 MB)
[ 0.000000] <0> pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB)
[ 0.000000] <0> .text : 0xc0008000 - 0xc0e68e4c (14724 kB)
[ 0.000000] <0> .init : 0xc0e69000 - 0xc0f24000 ( 748 kB)
[ 0.000000] <0> .data : 0xc0f24000 - 0xc109cb64 (1507 kB)
[ 0.000000] <0> .bss : 0xc109cb64 - 0xc1984998 (9120 kB)
[ 0.000000] <0>-(0)[0:swapper][name:cpu&][cpu_ntf] <00>c0157968 (slab_cpuup_callback)
[ 0.000000] <0>-(0)[0:swapper][name:slub&]SLUB: HWalign=64, Order=0-0, MinObjects=0, CPUs=4, Nodes=1
[ 0.000000] <0>-(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c005b0b0 (sched_ilb_notifier)
[ 0.000000] <0>-(0)[0:swapper/0][name:tree&]Preemptible hierarchical RCU implementation.
[ 0.000000] <0>-(0)[0:swapper/0][name:tree&] RCU debugfs-based tracing is enabled.
[ 0.000000] <0>-(0)[0:swapper/0][name:tree&] RCU restricting CPUs from NR_CPUS=8 to nr_cpu_ids=4.
[ 0.000000] <0>-(0)[0:swapper/0][name:tree&]RCU: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=4
[ 0.000000] <0>-(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c00b4200 (rcu_cpu_notify)
[ 0.000000] <0>-(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c02ab170 (radix_tree_callback)
[ 0.000000] <0>-(0)[0:swapper/0]NR_IRQS:508
[ 0.000000] <0>-(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c02cf528 (gic_secondary_init)
[ 0.000000] <0>-(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c00bbbd8 (timer_cpu_notify)
[ 0.000000] <0>-(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c00be8a8 (hrtimer_cpu_notify)
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_cpuxgpt&]cpuxgpt_r.start = 0x10200000
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_gpt&]mt_gpt_init: tmr_regs=0xe080a000, tmr_irq=184, freq=13000000
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_gpt&]gpt_devs_init: base_addr=0xe080a010
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_gpt&]gpt_devs_init: base_addr=0xe080a020
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_gpt&]gpt_devs_init: base_addr=0xe080a030
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_gpt&]gpt_devs_init: base_addr=0xe080a040
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_gpt&]gpt_devs_init: base_addr=0xe080a050
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_gpt&]gpt_devs_init: base_addr=0xe080a060
[ 0.000000] <0>-(0)[0:swapper/0][name:mt_gpt&]setup_clksrc1: dev->base_addr=0xe080a020 GPT2_CON=0x0
[ 0.000000] <0>-(0)[0:swapper/0][name:sched_clock&]sched_clock: 32 bits at 13MHz, resolution 76ns, wraps every 330382100403ns
[ 0.000023] <0>-(0)[0:swapper/0][name:mt_gpt&]setup_clksrc1: mt_cyclecounter.mult=0x99d89d8a mt_cyclecounter.shift=0x19
[ 0.000040] <0>-(0)[0:swapper/0][name:mt_gpt&]setup_clksrc2: dev->base_addr=0xe080a020 GPT2_CON=0x31
[ 0.000104] <0>-(0)[0:swapper/0][name:mt_gpt&]GPT1_CMP = 130000, HZ = 100
[ 0.000274] <0>-(0)[0:swapper/0][name:mt_cpuxgpt&]cpuxgpt_r.start = 0x10200000
[ 0.000312] <0>-(0)[0:swapper/0][name:mt_gpt&]mt_gpt_init: get_cnt_GPT2=3983
[ 0.000490] <0>-(0)[0:swapper/0][name:ca53_timer&]arch_timer_init:arch_timer_rate(0xc65d40),PHYS_SECURE_PPI=29,PHYS_NONSECURE_PPI=30,VIRT_PPI=27,HYP_PPI=26
[ 0.000510] <0>-(0)[0:swapper/0][name:ca53_timer&]arch_timer_register:arch_timer_rate(0xc65d40),arch_timer_use_virtual=0
[ 0.000542] <0>-(0)[0:swapper/0][name:ca53_timer&]arch_timer_register:request_percpu_irq PHYS_SECURE_PPI err=0
[ 0.000564] <0>-(0)[0:swapper/0][name:ca53_timer&]arch_timer_register:request_percpu_irq PHYS_NONSECURE_PPI err=0
[ 0.000584] <0>-(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c0352d30 (arch_timer_cpu_notify)
[ 0.001002] <0>-(0)[0:swapper/0][name:ca53_timer&]Architected cp15 timer(s) running at 13.00MHz (phys).
[ 0.001022] <0>-(0)[0:swapper/0][name:delay&]Switching to timer-based delay loop, resolution 76ns
[ 0.002199] <0>-(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c00d1780 (hotplug_cfd)
[ 0.092262] <0>.(0)[0:swapper/0][name:printk&]console [ttyMT1] enabled
[ 0.093119] <0>.(0)[0:swapper/0][name:mtk_ram_console&]ram_console: buffer start: 0xe081a000, size: 0x10000
[ 0.099636] <0>.(0)[0:swapper/0]Lock dependency validator: Copyright (c) 2006 Red Hat, Inc., Ingo Molnar
[ 0.100815] <0>.(0)[0:swapper/0]... MAX_LOCKDEP_SUBCLASSES: 8
[ 0.101542] <0>.(0)[0:swapper/0]... MAX_LOCK_DEPTH: 48
[ 0.102280] <0>.(0)[0:swapper/0]... MAX_LOCKDEP_KEYS: 8191
[ 0.103038] <0>.(0)[0:swapper/0]... CLASSHASH_SIZE: 4096
[ 0.103798] <0>.(0)[0:swapper/0]... MAX_LOCKDEP_ENTRIES: 16384
[ 0.104568] <0>.(0)[0:swapper/0]... MAX_LOCKDEP_CHAINS: 32768
[ 0.105338] <0>.(0)[0:swapper/0]... CHAINHASH_SIZE: 16384
[ 0.106108] <0>.(0)[0:swapper/0] memory used by lock dependency info: 3695 kB
[ 0.107020] <0>.(0)[0:swapper/0] per task-struct memory footprint: 1152 bytes
[ 0.107907] <0>.(0)[0:swapper/0][name:kmemleak&]kmemleak: Kernel memory leak detector disabled
[ 0.109007] [name:calibrate&]Calibrating delay loop (skipped), value calculated using timer frequency.. [name:calibrate&]26.00 BogoMIPS (lpj=130000)
[ 0.110663] <0>.(0)[0:swapper/0][name:pid&]pid_max: default: 32768 minimum: 301
[ 0.111856] <0>.(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c018f600 (buffer_cpu_notify)
[ 0.112851] <0>.(0)[0:swapper/0]Security Framework initialized
[ 0.113592] <0>.(0)[0:swapper/0]SELinux: Initializing.
[ 0.114949] <0>.(0)[0:swapper/0]Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.115993] <0>.(0)[0:swapper/0]Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.118432] <0>.(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c0124570 (ratelimit_handler)
[ 0.120347] CPU: Testing write buffer coherency: ok
[ 0.120987] <0>.(0)[0:swapper/0][name:cpu&][cpu_ntf] <00>c0029d54 (smpboot_thread_call)
[ 0.122998] <0>.(0)[1:swapper/0]CPU0: update cpu_capacity 1024
评语：MTK的LK代码和preloader代码写的非常混乱，各种宏定义乱入，不知道最近的代码有没有改善
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