Pandaboard data-acquisition and FPGA expansion

http://www.keteu.org/~haunma/proj/pandadaq/

Pandaboard data-acquisition and FPGA expansion
Motivation

Amateur scientists and other home experimenters often have difficulty finding data-acquisition (DAQ) hardware meeting their needs at reasonable cost. When PC sound-card I/O is not an option, commercial DAQ offerings in the sub-$200 range are quite limited and the most popular (e.g. National Instruments USB-6008) lack good Linux support.

The Pandaboard is ideal for this application because it is inexpensive, low-power, portable, runs Linux, and offers easy high-bandwidth expansion through the GPMC bus. On the older Beagleboard platform, the BeagleDaq project has similar goals but is limited to SPI communication with the host processor. The BeagleDaq also lacks timer/counter functions for accurately timed periodic sampling.

My first DAQ project was an 8-bit A/D and D/A with a Motorola 68230 Parallel Interface/Timer, hand-wired on an ISA-bus prototyping card back in high school. (Those were the days!) Nobody makes standalone timer/counter chips anymore; the modern solution is to put this inside an FPGA. After studying Eric Brombaugh's Beagleboard Tracker, an expansion board built around the Xilinx Spartan 3, a dual-use Pandaboard DAQ expansion and Tracker "refresh" seems reasonable. A Spartan 6 in 144-pin QFP can connect the A/Ds and D/As with the OMAP4 GPMC, with enough I/O left over to provide the Tracker-style Digilent-compatible headers. People wanting a basic FPGA dev board can populate just the FPGA and supporting hardware, while those needing DAQ functionality can mount the other parts too.
Design

The Panda DAQ will feature
Xilinx Spartan 6 FPGA in 144-pin QFP package (XC6SLX9-2TQG144C)
0-2 Analog Devices AD7606 8-channel, 16-bit, 200-ksps A/Ds
0-2 Analog Devices AD5064-1 4-channel, 16-bit D/As
Choice of 5.0x3.2mm 1.8V SMD clock oscillator, and optional OCXO for GPSDO experiments.
Jupiter F2 GPS module for sampling-clock calibration, timestamping, and location-aware data logging
Digital I/O: I2C, SPI, JTAG, some LEDs, and extra FPGA pins brought out to 8-bit Digilent-compatible headers (3.3V)
Battery-friendly switching power supply
FPGA configuration

The Panda DAQ follows the Tracker design, with an I2C parallel expander (TI TCA6408A, which runs at 1.8V) initiating slave-serial configuration and the OMAP McSPI sending the bitstream. The Spartan 6 simplifies the design by allowing configuration at 1.8V, eliminating some level shifters. Hopefully, we can leverage the Tracker configuration software with minimal changes.

After configuration, the FPGA should be able to communicate with the host over SPI, or set itself up on the GPMC bus.

Two I/O banks are taken up by the 1.8V GPMC, configuration I/Os, and clocks. The other two run at 3.3V and support the A/Ds, D/As, and I/O expansion headers. The DAQ hardware may limit the design to three 8-bit headers, versus four on the Tracker.
Power supplies

The board requires several voltage rails:
Voltage (V) Used by Est. current (mA) Source
1.2 FPGA core (Vccint) 500 SMPS (TPS62420)
1.8 FPGA + Pandaboard I/O (configuration and GPMC), GPS 100 Expansion connector
2.5 FPGA Vccaux 100 Linear regulator (TPS73625) from switcher 3.3V
3.3 FPGA I/O, oscillators, A/D and D/A digital interfaces 200 SMPS (TPS62420)
5.0 A/D and D/A 60 Expansion connector



A switching power supply adds complexity and risk, but given the low voltages required, the efficiency improvement is substantial. The TPS62420 is a dual switcher with few external components which can supply up to 1A for the 1.2V Vccint and up to 600 mA for the combined 3.3V and 2.5V rails. Voltage ramp-up after enable is compatible with the Spartan 6 requirement. The only drawback is the QFN package, but at least it's only ten pins.

The Pandaboard spec does not provide a limit for power drawn on the 1.8V expansion-connector pin, but comments on the mailing list suggest 100 mA is acceptable. If this turns out not to be true, another LDO hanging off the 3.3V switcher output should suffice.
Clocking and GPS

The I2C-programmable oscillator (LTC6904) from the Beagle Tracker is a nice part, but incompatible with a 1.8V I2C bus, and I couldn't find another comparable device.

The Spartan-6 CMTs (clock management tiles) include DLL clock multipliers and dividers, so a range of internal clocks can be generated from a simple fixed-frequency oscillator. 1.8V SMT oscillators are available in "standard" (25 ppm or worse), TCXO (temperature compensated: ~2 ppm), or VCTCXO (pullable +/- a few ppm with a control voltage) forms from multiple suppliers with compatible pinouts. The non-TC ones are available at Digikey, so the plan is to design for a standard four-pad 5.0x3.2mm oscillator and leave its selection to the end user.

The big oscillator companies advertise VCTCXOs at 1.8V or 3.3V, but only the oddball 3V parts are stocked at retail. If we can find a source for the "normal voltage" parts, they present interesting possibilities for calibration using the GPS pulse-per-second output with the oscillator control voltage wired to the on-board D/A. A proper GPS disciplined oscillator (GPSDO) is not really practical because the PPS signal typically has jitter of tens or hundreds of ns; the TCXO is not stable enough over the long averaging periods required to extract ppb accuracy from the GPS. (See this explanation.) Nevertheless, we can at least correct for medium-to-long-term drift. Much hinges on the PPS jitter distribution, but this is not specified.

24-Mar-11 update: Cheap OCXOs on Ebay! After failing to obtain samples or reasonable unit pricing on the Fox VCTCXOs, I found a bunch of 5V, 26-MHz surplus OCXOs with voltage control on Ebay for $2 apiece. I'm going to design these onto the board in addition to the little SMD oscillator. Operating current at room temperature is said to be 60 mA, and they are reasonably compact (14-pin DIP size).

Besides PPS, the Jupiter-F2 GPS module provides the usual time/location info via SPI, I2C, or plain UART. It runs from a single 1.8V supply and will talk to the FPGA using spare bank-2 IOs in SPI mode. It may be worthwhile to have a jumper-selectable connection to the Pandaboard UART4 pins, which are otherwise unused. The UART interface should be brought out to a header in any case, because the module is firmware upgradable with a Windows utility from SIRF (CSR).
A/D

I've followed the Beagle DAQ in selecting Analog Devices' 16-bit AD7606. The Panda DAQ will support up to two of these chips, each with eight channels which can be sampled simultaneously or in two groups at up to 200 kHz. The maximum sample rate is only intended for oversampling, and there is a fixed antialiasing filter with cutoff ~20 kHz. This is more than adequate for my use cases, although with the GPMC interface this board could make a nice software-defined-radio platform---if faster converters were used.

According to the datasheet, the analog inputs are single ended, but each channel has its own ground pin and it's not clear to me that these are tied internally, so some common-mode noise rejection may be possible.

The FPGA connects to the serial data lines and many control lines of each AD7606, allowing it to start conversions, choose the oversampling ratio, etc. independently on each chip. A precision reference (ADR421?) is designed in, but can be left unpopulated if the internal AD7606 reference is good enough. A jumper must be wired correctly to select internal versus external reference.
D/A

The D/As are Analog Devices' 16-bit AD5064-1. The analog outputs will be wired to a header alongside the reference input and 5V supply. The ref input can be bridged to 5V for non-critical applications, or the user can provide their own reference voltage.

The board has pads for two AD5064-1 parts. The serial interface supports daisy-chaining, so the serial data output of the first is connected to the input of the second.
Documentation
(18 Mar 2011) FPGA and expansion connector pin assignments
(28 Mar 2011) Draft schematic
(2 May 2011) Final(?) schematic and gEDA design files
(3 May 2011) Ready to begin PCB layout
Questions
Is it OK for the 1.8V rail to be powered when the other supplies are not (prior to enabling the switcher)? The i2c logic needs standby power, and the GPS will supposedly not wake up until a power-on signal from the FPGA. That leaves the Spartan 6 Vcco on two IO banks, which could be powered for a long time (potentially) before Vccint/Vccaux are applied and FPGA configuration begins. Xilinx spec says "no sequencing requirements" and lists Vcco quiescent current at 1 mA.
Answer: Xilinx says the only concern would be quiescent current from pullups on Vcco. No problem for us.
The Beagleboard Tracker had selectable 3.3 or 5 volts on the Digilent PMOD connectors. Spartan 6 does not support 5V I/O. Are there any Digilent boards that actually need 5V?
Answer: Very few PMODs require 5V.
Screw terminals (Phoenix Contact COMBICON, like National Instruments' boards) or traditional headers for the analog I/O?
Answer: I decided to leave these as double-row headers for now. The combicon strips are expensive, and though nice for some applications, unnecessary for many others.
Bring out analog-input grounds to the header separately, or tie together on the board? (Analog Devices says these are single-ended inputs.)
Answer: After a 3-week wait in the tech support queue, I received an answer which didn't quite satisfy my curiosity. The board will provide the individual AGNDs, though, because there is supposed to be a differential-input version of this part in the works.


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Last modified 3 May 2011 by haunma keteu org (insert punctuation).