【FPGA】基于bt1120时序设计实现棋盘格横纵向灰阶图数据输出

一、bt1120介绍

bt1120的标准时序为1080p@60hz，其一帧数据主要是由消隐和有效数据构成，有效数据为YCbCr 4：2：2方式输出，在数字行消隐还有两种定时基准码，一种在每个视频数据块的起始（SAV），另一种在每个视频数据块
的结束（EAV），其一帧数据还有两场和一场两种方式输出，一帧格式如下图所示。

逐行扫描系统中的帧时间期定时规范

图像定时基准码的比特分配
在EAV 和SAV输出，其格式如下，在这两个基准码前还有三个固定数据其格式为 ff 00 00 EAV、
ff 00 0 SAV.

二、代码

bt1120

module bt1120(//inputs
              clk,
              rst_n,
              data_in,
              
              //outputs
				hcnt,
				vcnt,
				hsync,
				vsync,
              data_out,
              clk_out
             );

input         clk;
input         rst_n;
input  [15:0] data_in;

output [11:0] hcnt;
output [10:0] vcnt;
output [15:0] data_out;
output          clk_out;
output          hsync;
output          vsync;


reg    [15:0] data_out;


parameter HNUM          = 12'd2200;  // 1080p @30Hz  2200  @25hz 2640
parameter VNUM          = 11'd1125;
parameter HSYNC_END     = 12'd276;
parameter VSYNC_START   = 11'd1121;
parameter VSYNC_END     = 11'd41;
parameter EAV           = 12'd4;
parameter SAV           = 12'd280;
parameter EAV_PRE       = 12'd1;
parameter SAV_PRE       = 12'd277;


assign clk_out = ~clk;

reg              hsync;
reg              vsync;
reg    [11:0]    hcnt;
reg    [10:0]    vcnt;

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
	  hcnt<=12'd1;
	  vcnt<=11'd1;
	end
	else if(hcnt==HNUM) begin
		hcnt<=12'd1;
		if(vcnt==11'd1125)
		  vcnt<=11'd1;
		else
		  vcnt<=vcnt+11'd1;
	end
	else
	  hcnt<=hcnt+12'd1;
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		hsync<=1'b0;
  else if(hcnt==HNUM)
    hsync<=1'b1;
  else if(hcnt==HSYNC_END)
    hsync<=1'b0;
  else
    ;
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		vsync<=1'b0;
  else if(hcnt==HNUM) begin
  	if(vcnt==VSYNC_START)
      vsync<=1'b1;
    else if(vcnt==VSYNC_END)
      vsync<=1'b0;
    else
      ;
  end
  else
    ;
end

assign p3 = 1'b0^vsync^hsync;
assign p2 = 1'b0^hsync;
assign p1 = 1'b0^vsync;
assign p0 = vsync^hsync;

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
	  data_out<=16'd0;
	else if(hcnt==SAV_PRE || hcnt==EAV_PRE)
	  data_out<=16'hffff;
	else if(hcnt==EAV || hcnt==SAV)
	  data_out<={1'b1,1'b0,vsync,hsync,p3,p2,p1,p0,1'b1,1'b0,vsync,hsync,p3,p2,p1,p0};
	else if(hcnt==SAV_PRE+12'd1 || hcnt==SAV_PRE+12'd2 || hcnt==EAV_PRE+12'd1 || hcnt==EAV_PRE+12'd2)
	  data_out<=16'd0;
	else if(hcnt==EAV+12'd1)
	  data_out<={~vcnt[6],vcnt[6:0],~vcnt[6],vcnt[6:0]};
	else if(hcnt==EAV+12'd2)
	  data_out<={4'b1000,vcnt[10:7],4'b1000,vcnt[10:7]};
	else if(hsync==1'b0 && vsync==1'b0)
	  data_out<=data_in;
	else
	  data_out<=16'h1080;
end



endmodule

下面展示一些 内联代码片。

test_img

module test_img(//inputs
                clk			,
                rst_n		,
                hcnt		,
                vcnt		,
				img_ctrl	,
                
                //outputs
                data_out	
               );
         
input           clk				;
input           rst_n			;
input  [11:0]   hcnt			;
input  [10:0]   vcnt			;
input  [3:0]    img_ctrl		;

output [15:0]   data_out		;

reg    [15:0]   data_out		;

/********************************************************/
reg    [15:0] 	data_checker	;
reg    [15:0] 	data_grayscale_c;
reg	   [15:0]	data_grayscale_l;



//输出
always @(*)begin 
	 if(img_ctrl == 4'b0000)begin				//checkerboard
	  data_out = data_checker;
	 end 
	 else if(img_ctrl == 4'b0001)begin 			//gray scale crosswise
	  data_out = data_grayscale_c;
	 end 
	 else if (img_ctrl == 4'b0010) begin		//gray scale lengthways
	  data_out = data_grayscale_l;	
	 end
	 else begin 
		data_out <= data_checker;
	 end 
end

//checkerboard
always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
	  data_checker<=1'b0;
	else if(vcnt[6]) begin
		if(hcnt[6])
	    data_checker<={8'd16,8'd128};//{8'd16,8'd128};16'ha040;
	  else
	    data_checker<={8'd235,8'd128};//{8'd235,8'd128};16'h60a0;
	end
	else begin
		if(hcnt[6])
	    data_checker<={8'd235,8'd128};//{8'd235,8'd128};16'h4050;
	  else
	    data_checker<={8'd16,8'd128};//{8'd16,8'd128};16'hb0c0;
	end
end


//gray scale
    //crosswise
reg 		[7:0]					cnt			;
wire 								add_cnt		;
wire								end_cnt		;

reg 		[3:0]					cnt_12		;
wire 								add_cnt_12	;
wire								end_cnt_12	;

always @(posedge clk or negedge rst_n)begin 
   if(!rst_n)begin
		cnt <= 8'd1;
	end 
	else if (hcnt == 12'd280) begin
		cnt <= 8'd1;
	end
	else if(add_cnt)begin 
			if(end_cnt)begin 
				cnt <= 8'd1;
			end
			else begin 
				cnt <= cnt + 8'd1;
			end 
	end
   else  begin
	   cnt <= cnt;
	end
end 

assign add_cnt = end_cnt_12;
assign end_cnt = add_cnt && cnt == 8'd160;


always @(posedge clk or negedge rst_n)begin 
   if(!rst_n)begin
		cnt_12 <= 4'd1;
	end 
	else if (hcnt == 12'd280) begin
		cnt_12 <= 4'd1;
	end
	else if(add_cnt_12)begin 
			if(end_cnt_12)begin 
				cnt_12 <= 4'd1;
			end
			else begin 
				cnt_12 <= cnt_12 + 4'd1;
			end 
	end
   else  begin
	   cnt_12 <= cnt_12;
	end
end 

assign add_cnt_12 = hcnt>12'd280;
assign end_cnt_12 = add_cnt_12 && cnt_12 == 4'd12;


always @(posedge clk or negedge rst_n)begin 
	if(!rst_n)begin
		data_grayscale_c <= 16'd0;
	end	
	else begin 
		data_grayscale_c <= {cnt,8'd128};
	end 
end

	//lengthways

reg 		[7:0]					cnt_l			;
wire 								add_cnt_l		;
wire								end_cnt_l		;

reg 		[3:0]					cnt_12_l		;
wire 								add_cnt_12_l	;
wire								end_cnt_12_l	;

always @(posedge clk or negedge rst_n)begin 
   if(!rst_n)begin
		cnt_l <= 8'd1;
	end 
	else if (vcnt == 11'd41) begin
		cnt_l <= 8'd1;
	end
	else if(add_cnt_l)begin 
			if(end_cnt_l)begin 
				cnt_l <= 8'd1;
			end
			else begin 
				cnt_l <= cnt_l + 8'd1;
			end 
	end
   else  begin
	   cnt_l <= cnt_l;
	end
end 

assign add_cnt_l = end_cnt_12_l;
assign end_cnt_l = add_cnt_l && cnt_l == 8'd108;


always @(posedge clk or negedge rst_n)begin 
   if(!rst_n)begin
		cnt_12_l <= 4'd1;
	end 
	else if (vcnt == 11'd41) begin
		cnt_12_l <= 4'd1;
	end
	else if(add_cnt_12_l)begin 
			if(end_cnt_12_l)begin 
				cnt_12_l <= 4'd1;
			end
			else begin 
				cnt_12_l <= cnt_12_l + 4'd1;
			end 
	end
   else  begin
	   cnt_12_l <= cnt_12_l;
	end
end 

assign add_cnt_12_l = vcnt>11'd41 && hcnt == 12'd2200;
assign end_cnt_12_l = add_cnt_12_l && cnt_12_l == 4'd10;


always @(posedge clk or negedge rst_n)begin 
	if(!rst_n)begin
		data_grayscale_l <= 16'd0;
	end 
	else begin 
		data_grayscale_l <= {cnt_l,8'd128};
	end 
end

三、bt1120中文建议书

https://blog.csdn.net/li_lys/article/details/124870664?utm_source=app&app_version=5.4.0&code=app_1562916241&uLinkId=usr1mkqgl919blen