HDLBits答案_Verilog Language_Modules: Hierarchy

1. Modules

Module - HDLBits

module top_module ( input a, input b, output out );
    
    mod_a u1 (.in1(a),.in2(b),.out(out)) ;

endmodule

2. Connecting ports by position

Module pos - HDLBits

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    
    mod_a instantiate1 (out1,out2,a,b,c,d);

endmodule

3. Connecting ports by name

Module name - HDLBits

module top_module ( 
    input a, 
    input b, 
    input c,
    input d,
    output out1,
    output out2
);
    
    mod_a instantiate2 (.out1(out1),.out2(out2),.in1(a),.in2(b),.in3(c),.in4(d));

endmodule

4. Three moudles

Module shift - HDLBits

module top_module ( input clk, input d, output q );
    
    wire q1,q2;
    my_dff instantiate1 (.clk(clk),.d(d),.q(q1));
    my_dff instantiate2 (.clk(clk),.d(q1),.q(q2));
    my_dff instantiate3 (.clk(clk),.d(q2),.q(q)); 

endmodule

5. Moudles and vectors

Module shift8 - HDLBits

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output reg [7:0] q 
);
    wire [7:0] q1,q2,q3;
    
    my_dff8 instantiate1 (.clk(clk), .d(d), .q(q1));
    my_dff8 instantiate2 (.clk(clk), .d(q1), .q(q2));
    my_dff8 instantiate3 (.clk(clk), .d(q2), .q(q3));
    
    always @(*) begin
        case (sel)
            2'b00: q=d;
            2'b01: q=q1;
            2'b10: q=q2;
            2'b11: q=q3;
            default: q=8'bxxxx_xxxx;
        endcase
    end
    
endmodule

6. Adder 1

Module add - HDLBits

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire cout_low;
    
    add16 instantiate1 (.a(a[15:0]), .b(b[15:0]), .sum(sum[15:0]), .cout(cout_low));
    
    add16 instantiate2 (.a(a[31:16]), .b(b[31:16]), .cin(cout_low), .sum(sum[31:16])); 

endmodule

7. Adder 2

Module fadd - HDLBits

module top_module (
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);//
    wire cout_low16;
    add16 instantiate1 (.a(a[15:0]),.b(b[15:0]),.sum(sum[15:0]),.cout(cout_low16));
    add16 instantiate2 (.a(a[31:16]),.b(b[31:16]),.cin(cout_low16),.sum(sum[31:16]));

endmodule

module add1 ( input a, input b, input cin,   output sum, output cout );

// Full adder module here
    assign sum = a^b^cin;
    assign cout = (a&b)|(a&cin)|(b&cin);

endmodule

8. Carry-select adder

Module cseladd - HDLBits

module top_module(
    input [31:0] a,
    input [31:0] b,
    output [31:0] sum
);
    wire co_l;
    wire [15:0] sum0,sum1;
    
    add16 instantiate1 (.a(a[15:0]), .b(b[15:0]), .sum(sum[15:0]),.cout(co_l)     );
    add16 instantiate2 (.a(a[31:16]),.b(b[31:16]),.cin(1'b0),     .sum(sum0[15:0]));
    add16 instantiate3 (.a(a[31:16]),.b(b[31:16]),.cin(1'b1),     .sum(sum1[15:0]));
    
    always @(*)
        case (co_l)
            1'b0: sum[31:16] = sum0[15:0];
            1'b1: sum[31:16] = sum1[15:0];
            default: sum[31:16] = 16'h0000;
        endcase
    
endmodule

9. Adder-subtractor

Module addsub - HDLBits

module top_module(
    input [31:0] a,
    input [31:0] b,
    input sub,
    output [31:0] sum
);
    wire [31:0] b_;
    wire co_l;
    
    assign b_ = b^{32{sub}};
    
    add16 instantiate1 (.a(a[15:0]), .b(b_[15:0]), .cin(sub), .sum(sum[15:0]),.cout(co_l));
    add16 instantiate2 (.a(a[31:16]),.b(b_[31:16]),.cin(co_l),.sum(sum[31:16])           );

endmodule