12、STM32MP157A-有线网卡驱动移植

STM32MP157A 系列 SoC 集成一个千兆以太网媒体访问控制器，支持 RMII 和 MII 两种标准的 PHY，FS-MP1A 设备上外接了一个瑞昱的千兆以太网 PHY 芯片 RTL8211F，原理图如下：

查看原理图得出 RTL8211F 数据管脚与 STM32MP157A 的管脚对应关系如下：
（1）网卡设备节点
参考文档：
Documentation/devicetree/bindings/net/stm32-dwmac.txt
Documentation/devicetree/bindings/net/ethernet-controller.yaml
Documentation/devicetree/bindings/net/ethernet-phy.yaml
Documentation/devicetree/bindings/net/snps,dwmac.yam
内核中 ST 对 STM32MP15x 系列芯片的设备树资源了做了定义，可参见：
arch/arm/boot/dts/stm32mp151.dtsi
stm32mp151 中 ethernet 定义如下：

ethernet0: ethernet@5800a000 {
    compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
    reg = <0x5800a000 0x2000>;
    reg-names = "stmmaceth";
    interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
                          <&exti 70 IRQ_TYPE_LEVEL_HIGH>;
    interrupt-names = "macirq",
                      "eth_wake_irq";
    clock-names = "stmmaceth",
                  "mac-clk-tx",
                  "mac-clk-rx",
                  "ethstp";
    clocks = <&rcc ETHMAC>,
                 <&rcc ETHTX>,
                 <&rcc ETHRX>,
                 <&rcc ETHSTP>;
    st,syscon = <&syscfg 0x4>;
    snps,mixed-burst;
    snps,pbl = <2>;
    snps,en-tx-lpi-clockgating;
    snps,axi-config = <&stmmac_axi_config_0>;
    snps,tso;
    power-domains = <&pd_core>;
    status = "disabled";
};

上述代码只对 ethernet 做了基本的初始化，并没有针对不同的硬件设计做适配，所以需结合硬件补全设备树节点信息。
对照内核文档目录下相关文档添加补充相关信息，亦可参考内核中其他设备树文件中相关描述，比如 stm32mp15xx-dkx.dtsi 关于 ethernet 的描述符合我们的要求，内容如下：

&ethernet0 {
    status = "okay";
    pinctrl-0 = <ðernet0_rgmii_pins_a>;
    pinctrl-1 = <ðernet0_rgmii_pins_sleep_a>;
    pinctrl-names = "default", "sleep";
    phy-mode = "rgmii-id";
    max-speed = <1000>;
    phy-handle = <&phy0>;
    mdio0 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "snps,dwmac-mdio";
        phy0: ethernet-phy@0 {
            reg = <0>;
        };
    };
};

（2）管脚定义
在内核中 STM32MP1 默认管脚定义在文件 arch/arm/dts/stm32mp15-pinctrl.dtsi 中，查看文件中是否有需要的管脚定义：
查看后确认有 ethernet 的管脚定义，且与 FS-MP1A 硬件使用情况一致，定义如下：

ethernet0_rgmii_pins_a: rgmii-0 {
    pins1 {
        pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
        <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
        <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
        <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
        <STM32_PINMUX('C', 2, AF11)>, /* ETH_RGMII_TXD2 */
        <STM32_PINMUX('E', 2, AF11)>, /* ETH_RGMII_TXD3 */
        <STM32_PINMUX('B', 11, AF11)>, /* ETH_RGMII_TX_CTL */
        <STM32_PINMUX('C', 1, AF11)>; /* ETH_MDC */
        bias-disable;
        drive-push-pull;
        slew-rate = <2>;
    };
    pins2 {
        pinmux = <STM32_PINMUX('A', 2, AF11)>; /* ETH_MDIO */
        bias-disable;
        drive-push-pull;
        slew-rate = <0>;
    };
    pins3 {
        pinmux = <STM32_PINMUX('C', 4, AF11)>, /* ETH_RGMII_RXD0 */
        <STM32_PINMUX('C', 5, AF11)>, /* ETH_RGMII_RXD1 */
        <STM32_PINMUX('B', 0, AF11)>, /* ETH_RGMII_RXD2 */
        <STM32_PINMUX('B', 1, AF11)>, /* ETH_RGMII_RXD3 */
        <STM32_PINMUX('A', 1, AF11)>, /* ETH_RGMII_RX_CLK */
        <STM32_PINMUX('A', 7, AF11)>; /* ETH_RGMII_RX_CTL */
        bias-disable;
    };
};
ethernet0_rgmii_pins_sleep_a: rgmii-sleep-0 {
    pins1 {
        pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
        <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
        <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
        <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
        <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_TXD2 */
        <STM32_PINMUX('E', 2, ANALOG)>, /* ETH_RGMII_TXD3 */
        <STM32_PINMUX('B', 11, ANALOG)>, /* ETH_RGMII_TX_CTL */
        <STM32_PINMUX('A', 2, ANALOG)>, /* ETH_MDIO */
        <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_MDC */
        <STM32_PINMUX('C', 4, ANALOG)>, /* ETH_RGMII_RXD0 */
        <STM32_PINMUX('C', 5, ANALOG)>, /* ETH_RGMII_RXD1 */
        <STM32_PINMUX('B', 0, ANALOG)>, /* ETH_RGMII_RXD2 */
        <STM32_PINMUX('B', 1, ANALOG)>, /* ETH_RGMII_RXD3 */
        <STM32_PINMUX('A', 1, ANALOG)>, /* ETH_RGMII_RX_CLK */
        <STM32_PINMUX('A', 7, ANALOG)>; /* ETH_RGMII_RX_CTL */
    };
};

（3）修改步骤
导入交叉编译工具链

source /opt/st/stm32mp1/3.1-openstlinux-5.4-dunfell-mp1-20-06-24/environment-setup-cortexa7t2hf-neon-vfpv4-ostl-linux-gnueabi

添加 MAE0621A 网卡驱动
FS-MP1A V3.0 版本配套网卡主控芯片是 MAE0621A，内核中并没有提供其的驱动，所以需要移植 MAE0621A 的驱动
将phy_device.c 和 maxio.c 文件复制到内核源码下的 drivers/net/phy/目录下。
由于在原内核中并没有 maxio.c 文件的编译选项，这里我们需要在内核中添加对应的编译选项。主要涉及 drivers/net/phy/目录下的 Kconfig 和 Makefile 两个配置文件。在 drivers/net/phy/Kconfig 文件中添加 MAE0621A 驱动的配置项。（make menuconfig配置项）

config REALTEK_PHY
     tristate "Realtek PHYs"
     ---help---
     Supports the Realtek 821x PHY.
config MAXIO_PHY
     tristate "MAXIO PHYS"
     ---help---
     Supports the Maxio MAEXXXX PHY.
config RENESAS_PHY
     tristate "Driver for Renesas PHYs"

在 drivers/net/phy/Makefile 文件中添加 MAE0621A 驱动的编译项。

obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o 
obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o
obj-$(CONFIG_MAXIO_PHY) += maxio.o

由于 phy_device.c 文件在原内核源码中已经存在此文件这里不需要再添加配置选项。
添加网卡设备树配置。
修改 arch/arm/boot/dts/stm32mp15xx-fsmp1x.dtsi 文件
在文件末尾添加如下内容：

&ethernet0 {
    status = "okay";
    pinctrl-0 = <&ethernet0_rgmii_pins_a>;
    pinctrl-1 = <&ethernet0_rgmii_pins_sleep_a>;
    pinctrl-names = "default", "sleep";
    phy-mode = "rgmii-id";
    max-speed = <1000>;
    phy-handle = <&phy0>;
    mdio0 {
        #address-cells = <1>;
        #size-cells = <0>;
        compatible = "snps,dwmac-mdio";
        phy0: ethernet-phy@0 {
        reg = <0>;
        };
    };
};

配置内核
由于内核源码默认配置以及支持网卡，本节列出主要选项，如下：
make menuconfig

Device Drivers --->
    [*] Network device support --->
        [*] Ethernet driver support --->
        <*> STMicroelectronics Multi-Gigabit Ethernet driver
        <*> STMMAC Platform bus support
        <*> Support for snps,dwc-qos-ethernet.txt DT binding.
        <*> Generic driver for DWMAC
        <*> STM32 DWMAC support

添加 MAE0621A 驱动

Device Drivers --->
    [*] Network device support --->
         -*- PHY Device support and infrastructure --->
        < > Quality Semiconductor PHYs
        <*> Realtek PHYs
        <*> MAXIO PHYS
        < > Driver for Renesas PHYs

（4）编译内核及设备树
make -j4 uImage dtbs LOADADDR=0xC2000040

cp arch/arm/boot/uImage /tftpboot/
cp arch/arm/boot/dts/stm32mp157a-fsmp1a.dtb /tftpboot/
cp arch/arm/boot/dts/stm32mp157a-fsmp1a*.dtb /tftpboot/