0. 介绍
字面值(literal integer)就是类似5、'h10这种值。
1. syntax
<size>'s<base><value>
- <size> is optional. If given, it specifies the total number of bits represented by the literal integer. If not given, the default size, per the Verilog/SystemVerilog standard is "at least"32 bits.
- s is optional. If given, it specifies thatthe literal integer should be treated as a signed value in operations. If not given, the default is unsigned. (The signed specifier wasadded to Verilog as part of the Verilog-200I standard.)
- <base> is required, and specifies whether the value is in binary, octal, decimal, or hex.
- <value> is required, andspecifies the literal integer value.
The baseoptions are represented using b, 0, d, or h for binary, octal, decimal andhex,
respectively. The base specifier can be either lowercase or uppercase (i.e. ' h 5
and ' H5 are the same).
2. 符号
Unbased literal integers default to signed. Based literal integers default to unsigned.
比如5,表示有符号的5;'d5表示无符号5.
3. 例子
byte in; // signed a-bit variables
int outl, out2; // signed 32~bit variables
initial begin
in ==-5;
out1 = in + 1; // OK: -5 + 1 = -4 (literal 1 is signed)
out2 = in + 1'b1; // GOTCHA: -5 +1'b1 = 252 (1'b1 is unsigned)
end
- 负数的运算先转化成补码,补码计算之后再转换成原码。
负数补码=(符号位不变)其他位按位取反+1;
负数原码=(符号位不变)-1之后,按位取反;
正数补码=原码;
所以out1 = in+1=(11111011)补 + (1)补 = (11111100)补 = (10000100)原 = -4(十进制)
- 负数和正数运算
负数会被当做正数,即负数in的补码(11111011)被当做正的251,所以out2为252.
3. reference
《Verilog and SystemVerilog Gotchas》