2021-09-01

FPGA的verilog实现自动售货机带找零。

   该售货机的商品每件都是2.5元，每次只能投入1元或者0.5元，若投入3元时，可设找零状态。
   首先设六个状态，分别为0状态，0.5元，1元，1.5元，2元，找0状态。
   代码如下：module fsm(

input wire rst_n,
input wire clk,
input wire [1:0]money,
output reg cola,
output reg _five );
reg [5:0]state;
parameter IDLE = 6’b00_0001;
parameter F_IVE = 6’b00_0010;
parameter ONE = 6’b00_0100;
parameter ONE_FIVE = 6’b00_1000;
parameter TWO = 6’b01_0000;
parameter ZHAO = 6’b10_0000;
always @(posedge clk or negedge rst_n) begin if (rst_n == 1’b0) begin
state<=IDLE;
end else begin
case(state)
IDLE:if(money == 'd1)
state<=F_IVE;
else if(money == 'd2)
state<=ONE;
F_IVE:if(money == 'd1)
state<=ONE;
else if(money == 'd2)
state<=ONE_FIVE;
ONE:if(money == 'd1)
state<=ONE_FIVE;
else if(money == 'd2)
state<=TWO;
ONE_FIVE:if(money == 'd1)
state<=TWO;
else if(money == 'd2)
state<=IDLE;
TWO:if(money == 'd1)
state<=IDLE;
else if(money == 'd2)
state<=ZHAO;
ZHAO:state<=IDLE;
default:state<=IDLE;
endcase
end
end
always @(posedge clk or negedge rst_n) begin
if (rst_n == 1’b0) begin
cola<=1’b0;
end
else if (state == ONE_FIVE && money == 'd2)begin
cola<=1’b1;
end
else if (state == TWO && money == 'd1) begin cola<=1’b1;
end
else if (state == ZHAO) begin
cola<=1’b1; _five<=1’b1;
end
else begin
cola<=1’b0;
_five<=1’b0;
end
end
endmodule