21、ila

1、bd文件中添加debug信号，右击信号线，debug。

2、使用(*mark_debug = "true"*)，

        增加新的debug信号时，需将xdc文件中上一次自动生成的语句删除，重新综合；综合完重新set up debug，再实现、生成bit流，否则新增加的debug信号不生效；

3、以下语句提示ram资源不足：

[DRC UTLZ-1] Resource utilization: RAMB18 and RAMB36/FIFO over-utilized in Top Level Design (This design requires more RAMB18 and RAMB36/FIFO cells than are available in the target device. This design requires 296 of such cell types but only 280 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)