Verilog基础知识（简单的时序逻辑）

寄存器

同步时序电路设计风格下建议所有的输出都是reg型，也就是最后的输出要有一个寄存器（边沿触发）。
常用的寄存器有不带置位和重置的简单DFF，异步置位同步释放的DFF，异步置位重置同步释放的DFF。

module FlipFlops(
    input D, clk, rst, pst,
    output reg Qsimple, Qasyncrst, Qasyncpst
    );

// simple DFF
always @(posedge clk)
    Qsimple <= D;

// asynchronous reset, synchronous release
always @(posedge clk, posedge rst)begin
    if (rst == 1'b1)
        Qasyncrst <= 1'b0;
    else
        Qasyncrst <= D;
end

// asynchronous reset/preset, synchronous release
always @(posedge clk, posedge rst, posedge pst)begin
    if (rst == 1'b1)
        Qasyncpst <= 1'b0;
    else if (pst == 1'b1)
        Qasyncpst <= 1'b1;
    else
        Qasyncpst <= D;
end

endmodule

`timescale 1ns/100ps

module FlipFlops_tb;

reg D, clk, rst, pst;
wire Qsimple, Qasyncrst, Qasyncpst;

FlipFlops FF_U1(
    .D(D),
    .clk(clk),
    .rst(rst),
    .pst(pst),
    .Qsimple(Qsimple),
    .Qasyncrst(Qasyncrst),
    .Qasyncpst(Qasyncpst)
    );

always #1 clk = ~clk;

initial begin
    #0
        clk = 1'b1;
        D = 1'b0;
        rst = 1'b0;
        pst = 1'b0;