Notes: Hardware-based Acceleration Design 20200219

7. FIFO

7.1. Full and Empty

7.1.1. Full but no more input

7.1.2. Empty but no more output

Solution: an extra bit to identify the same cycle.

Gray code for less meta-stability.

7.2. Depth Design

8. Reset

8.1. Synchronized Reset for clock circuit

8.2. Asynchronized Reset for Combination Logic

9. State Machine

9. Two-/Three-section FSM Definition