timing verification---虚假路径

It is possible that certain timing paths are not real (or not possible) in the actual functional operation of the design. Such paths can be turned off during STA by setting these as false paths. A false path is ignored by the STA for analysis.

The advantage of identifying the false paths is that the analysis space is reduced, thereby allowing the analysis to focus only on the real paths. This helps cut down the analysis time as well.However, too many false paths which are wildcarded using the through specification can slow down the analysis.

Few recommendations on setting false paths are given below. To set a false path between two clock domains, use:
set_false_path -from [get_clocks clockA] \
-to [get_clocks clockB]
instead of:
set_false_path -from [get_pins {regA_*}/CP] \
-to [get_pins {regB_*}/D]

The second form is much slower.

Another recommendation is to minimize the usage of -through options, as it adds unnecessary runtime complexity. The -through option should only be used where it is absolutely necessary and there is no alternate way to specify the false path.

From an optimization perspective, another guideline is to not use a false path when a multicycle path is the real intent. If a signal is sampled at a known or predictable time, no matter how far out, a multicycle path specification should be used so that the path has some constraint and gets optimized to meet the multicycle constraint. If a false path is used on a path that is sampled many clock cycles later, optimization of the remaining logic may invariably slow this path even beyond what may be necessary.