转自:http://blog.csdn.net/xiaojianpitt/article/details/7613489
CPU性能衡量参数-主频,MIPS,CPI,时钟周期,机器周期,指令周期
1,主频
主频 = 时钟频率,它是指CPU内部晶振的频率,常用单位为MHz,它反映了CPU的基本工作节拍;
时钟频率又称主频,它是指CPU内部晶振的频率,常用单位为MHz,它反映了CPU的基本工作节拍;
2,时钟周期
时钟周期 t =1/ f; 主频的倒数
3,机器周期
机器周期 = m*t ;一个机器周期包含若干个时钟周期
4,指令周期
指令周期 = m*t*n; 执行一条指令所需要的时间,一般包含若干个机器周期
5,CPI
CPI = m*n; 平均每条指令的平均时钟周期个数
指令周期 = CPI×机器周期 = n(CPI=n)×m×时钟周期=nm/主频f, 注意指令周期单位是s或者ns,CPI无量纲
参考:https://en.wikipedia.org/wiki/Cycles_per_instruction
6,MIPS(MillionInstructions Per Second)
MIPS = 每秒执行百万条指令数 = 1/(CPI×时钟周期)= 主频/CPI
MFLOPS 每秒百万浮点运算次数。
表示秒钟所能执行的指令条数,对于微型计算机可用CPU的主频和每条指令的执行所需的时钟周期来衡量。
包含关系:指令周期通常用若干个机器周期来表示,在机器语言中,使用执行一条指令所需要的机器周期数来说明指令执行的速度。而机器周期又包含若干个时钟周期。时钟周期是最基本的操作单位。
参考: https://en.wikipedia.org/wiki/Instructions_per_second
注意:计算机的运算速度一般用每秒钟所能执行的指令条数来表示。由于不同类型的指令所需时间长度不同,因而运算速度的计算方法也不同。例如,根据不同类型的指令出现的频度,乘上不同的系数求得统计平均值,得到平均运算速度。这种方法用MIPS(Millions of Instruction Per Second)作单位,即每秒百万条指令。
又如,直接给出CPU的主频和每条指令的执行所需的时钟周期。周期一般以MHz为单位。主频即计算机的时钟频率,它在很大程度上决定了主机的工作速度。例如,型号为486DX-133的微型计算机,表明它的CPU型号为486,DX为含浮点处理器,数字133的含义是主频为133MHz。
题: 若某处理器的时钟频率为500MHz,每4个时钟周期组成一个机器周期,执行一条指令需要3个机器周期,则该处理器的一个机器周期▁8▁ns,平均执行速度为▁42▁MIPS
解析如下:
时钟周期T等于主频的倒数,即T=1/500MHz=1/(0.5×10的9次方Hz)=2 ns,机器周期等于4个时钟周期即=4T=4×2 ns=8 ns,每条指令的时钟周期数CPI=3×4=12,则平均速度为:f/(CPI×10的6次方)=(500×10的6次方)/(12×10的6次 方)=500/12=41.6≈42MIPS.计算主频的倒数时要注意把主频的MHz换算成Hz即500后面加6个0=500×10的6次方=0.5×10的9次方,1/10的9次方 Hz=1ns
每条指令的时钟周期数CPI=3×4=12,执行一条指令需要3个机器周期数,一个机器周期包含4个时钟周期,所以CPI=3×4=12,这里计算 的都是周期的个数,和具体的时间ns纳秒没有关系,若带上具体的时间,一个时钟周期T=2ns,一个机器周期就是2×4=8ns,执行一条指令需要三个机 器周期得出执行一条指令需要的具体时间为3×8=24ns,执行每条指令的需要的时钟周期数CPI换句话说就是把执行每条指令需要的时间24ns换算成时 钟周期个数表示,为多少个时钟周期个数?时钟周期是最基本的时间操作单位,500MHz主频的处理器一个时钟周期为2ns,24ns等于多少个时钟周期?24/2=12个时钟周期,即那一句:“每条指令的时钟周期数CPI=12”。
另一个例子:
A 40-MHzprocessor was used to execute a benchmarkprogram with the following instruction mix and clockcycle count:
Instruction type | Instruction count | Clock cycle count |
Integer arithmetic | 45000 | 1 |
Data transfer | 32000 | 2 |
Floating point | 15000 | 2 |
Control transfer | 8000 | 2 |
Determine the effective CPI, MIPS rate, and execution time for thisprogram.
Total instructioncount = 100000.
CPI = (45000*1 +32000*2 + 15000*2 + 8000*2)/100000 = 155000/100000 = 1.55.
MIPS = clockfrequency/(CPI*1000000) = (40*1000000)/(1.55*1000000) = 25.8.
Therefore:
Execution time (T)= CPI*Instruction count*clock time = CPI*Instruction count/frequency =1.55*100000/40000000 = 1.55/400 = 3.87 ms.
IPS演进时间表
处理器 | IPS | IPS/MHz | 年份 | 来源 |
笔算(用于比较) | 0.0119 IPS | n/a | 1892 | |
92 kIPS at 740 kHz[2] | 0.124 | 1971 | ||
IBM System/370 model 158-3 | 1 MIPS | 1 | 1972 | |
640 kIPS at 2 MHz | 0.32 MIPS/MHz | 1974 | ||
500 kIPS | 0.5 | 1977 | ||
1 MIPS at 8 MHz | 0.125 MIPS/MHz | 1979 | ||
2.66 MIPS at 12 MHz | 0.22 MIPS/MHz | 1982 | ||
4 MIPS at 20 MHz | 0.2 MIPS/MHz | 1984 | ||
4 MIPS at 8 MHz | 0.5 MIPS/MHz | 1986 | ||
11 MIPS at 33 MHz | 0.33 MIPS/MHz | 1987 | ||
8.5 MIPS at 25 MHz | 0.34 MIPS/MHz | 1988 | ||
44 MIPS at 40 MHz | 1.1 MIPS/MHz | 1990 | ||
54 MIPS at 66 MHz | 0.818 MIPS/MHz | 1992 | ||
88 MIPS at 66 MHz | 1.33 MIPS/MHz | 1994 | ||
541 MIPS at 200 MHz | 2.705 MIPS/MHz | 1996 | ||
35.9 MIPS at 40 MHz | 0.897 MIPS/MHz | 1996 | ||
525 MIPS at 233 MHz | 2.253 MIPS/MHz | 1997 | ||
80 MIPS at 50 MHz | 1.6 MIPS/MHz | 1999 | ||
1,354 MIPS at 500 MHz | 2.708 MIPS/MHz | 1999 | ||
760 MIPS at 400 MHz | 1.9 MIPS/MHz | 2000 | [6] Integrated Communications Processors | |
3,561 MIPS at 1.2 GHz | 2.967 MIPS/MHz | 2000 | ||
5,935 MIPS at 2.0 GHz | 2.967 MIPS/MHz | 2002 | ||
9,726 MIPS at 3.2 GHz | 3.039 MIPS/MHz | 2003 | ||
2,000 MIPS at 1.0 GHz | 2.0 MIPS/MHz | 2005 | ||
12,000 MIPS at 2.8 GHz | 4.285 MIPS/MHz | 2005 | ||
14,564 MIPS at 2.0 GHz | 7.282 MIPS/MHz | 2005 | ||
19,200 MIPS at 3.2 GHz | 2.0 MIPS/MHz | 2005 | ||
PS3 Cell BE (PPE only) | 10,240 MIPS at 3.2 GHz | 3.2 MIPS/MHz | 2006 | |
18,938 MIPS at 2.6 GHz | 7.283 MIPS/MHz | 2006 | ||
27,079 MIPS at 2.93 GHz | 9.242 MIPS/MHz | 2006 | ||
49,161 MIPS at 2.66 GHz | 18.481 MIPS/MHz | 2006 | ||
8,800 MIPS at 2.0 GHz | 4.4 MIPS/MHz | 2007 | ||
59,455 MIPS at 3.2 GHz | 18.580 MIPS/MHz | 2008 | ||
76,383 MIPS at 3.2 GHz | 23.860 MIPS/MHz | 2008 | ||
42,820 MIPS at 3.0 GHz | 14.273 MIPS/MHz | 2009 |
Timeline of instructions per second
Processor | Dhrystone MIPS | D IPS / clock cycles per second | D IPS / clock cycles per second / Cores per die | Year | Source |
92 kIPS at 740 kHz | 0.1 | 0.1 | 1971 | ||
IBM System/370 model 158-3 | 1 Dhrystone MIPS | 1.0 | 0.1 | 1972 | |
500 kIPS at 2 MHz | 0.3 | 0.3 | 1974 | ||
500 kIPS at 1 MHz | 0.5 | 0.5 | 1975 | ||
500 kIPS at 5 MHz | 0.2 | 0.2 | 1977 | ||
1 MIPS at 8 MHz | 0.1 | 0.1 | 1979 | ||
2.66 MIPS at 12.5 MHz | 0.2 | 0.2 | 1982 | ||
4 MIPS at 20 MHz | 0.2 | 0.2 | 1984 | ||
11.4 MIPS at 33 MHz | 0.3 | 0.3 | 1985 | ||
4 MIPS at 8 MHz | 0.5 | 0.5 | 1986 | ||
11 MIPS at 33 MHz | 0.3 | 0.3 | 1987 | ||
44 MIPS at 40 MHz | 1.1 | 1.1 | 1990 | ||
300 MIPS at 150 MHz | 2.0 | 2.0 | 1992 | ||
54 MIPS at 66 MHz | 0.8 | 0.8 | 1992 | ||
88 MIPS at 66 MHz | 1.33 | 1.33 | 1994 | ||
188 MIPS at 100 MHz | 1.88 | 1.88 | 1994 | ||
5 MIPS at 20 MHz | 0.25 | 0.25 | 1995 | ||
16 MIPS at 16 MHz | 1 | 1 | 1996 | ||
35.9 MIPS at 40 MHz | 0.9 | 0.9 | 1996 | ||
541 MIPS at 200 MHz | 2.7 | 2.7 | 1996 | ||
525 MIPS at 233 MHz | 2.3 | 2.3 | 1997 | ||
80 MIPS at 50 MHz | 1.6 | 1.6 | 1999 | ||
2,054 MIPS at 600 MHz | 3.4 | 3.4 | 1999 | ||
760 MIPS at 400 MHz | 1.9 | 1.9 | 2000 | [11] Integrated Communications Processors | |
3,561 MIPS at 1.2 GHz | 3.0 | 3.0 | 2000 | ||
7,527 MIPS at 1.83 GHz | 4.1 | 4.1 | 2003 | ||
9,726 MIPS at 3.2 GHz | 3.0 | 3.0 | 2003 | ||
356 MIPS at 233 MHz | 1.5 | 1.5 | 2004 | ||
1 MIPS at 4 MHz | 0.25 | 0.25 | 2004 | ||
125 MIPS at 100MHz | 1.25 | 1.25 | 2004 | ||
Nios II/f | 190 MIPS at 165 MHz | 1.13 | 1.13 | 2004 | |
2,000 MIPS at 1.0 GHz | 2.0 | 2.0 | 2005 | ||
1,799 MIPS at 1.3 GHz | 1.4 | 1.4 | 2005 | ||
12,000 MIPS at 2.8 GHz | 4.3 | 4.3 | 2005 | ||
14,564 MIPS at 2.0 GHz | 7.3 | 3.6 | 2005 | ||
19,200 MIPS at 3.2 GHz | 6.0 | 2.0 | 2005 | ||
PS3 Cell BE (PPE only) | 10,240 MIPS at 3.2 GHz | 3.2 | 3.2 | 2006 | |
18,938 MIPS at 2.6 GHz | 7.3 | 3.6 | 2006 | ||
27,079 MIPS at 2.93 GHz | 9.2 | 4.6 | 2006 | ||
49,161 MIPS at 2.66 GHz | 18.4 | 4.6 | 2006 | ||
604 MIPS at 400 MHz | 1.51 | 1.51 | 2006 | ||
450 MIPS at 270 MHz | 1.66 | 1.66 | 2006 | ||
1,370 MIPS at 600 MHz | 2.3 | 2.3 | 2007 | ||
3,084 MIPS at 1.8 GHz | 4.4 | 4.4 | 2007 | ||
59,455 MIPS at 3.2 GHz | 18.6 | 4.6 | 2008 | ||
82,300 MIPS at 2.66 (Turbo 2.93) GHz | 30.9 | 7.7 | 2008 | ||
3,846 MIPS at 1.6 GHz | 2.4 | 1.2 | 2008 | ||
45 MIPS at 50MHz | 0.9 | 0.9 | 2009 | ||
5,000 MIPS at 1.0 GHz | 5.0 | 2.5 | 2009 | ||
10,000 MIPS at 1.6 GHz | 6.25 | 3.125 | 2011 | ||
42,820 MIPS at 3.0 GHz | 14.3 | 3.5 | 2009 | ||
78,440 MIPS at 3.3 GHz | 23.7 | 3.9 | 2010 | ||
35,000 MIPS at 2.5 GHz | 14.0 | 3.5 | 2010 | ||
147,600 MIPS at 3.33 GHz | 44.7 | 7.46 | 2010 | ||
128,300 MIPS at 3.4 GHz | 37.7 | 9.43 | 2011 | ||
92,100 MIPS at 2.93 GHz | 31.4 | 7.85 | 2011 | ||
108,890 MIPS at 3.6 GHz | 30.2 | 3.78 | 2011 | ||
515 MIPS at 412 MHz | 1.25 | 1.25 | 2002 | ||
2,850 MIPS at 1.5 GHz | 1.9 | 1.9 | 2011 | ||
2,100 MIPS at 1 GHz | 2.1 | 2.1 | 2008 | ||
9,900 MIPS at 1.5 GHz | 6.6 | 3.3 | 2011 | ||
177,730 MIPS at 3.33 GHz | 53.3 | 8.89 | 2011 |