vivado 解决 module ‘design_1_v_tpg_0_v_tpg‘ not found

SOLUTION

This issue is due to a difference between Project and Non-project mode and how HLS based IP are handled.

The generate_target command will usually take care of creating all of the HDL files needed for synthesis.

However, for design that contain an HLS IP core (V_tpg in the example above), the flow requires the compile_c command to be run in order to generate the needed HDL from the C code that is delivered during generation. 

In project mode, the compile_c command is run automatically but in non-project mode a user will need to insert it between target generation and synthesis.

If you are unsure which, if any, IP cores in the project are HLS based, you can also just run compile_c on all of the IP

foreach ip_in_proj [get_ips] {compile_c [get_ips $ip_in_proj]}

from :
70400 - Vivado IP Flows - Synthesizing a Block design in non-project mode fails with ERROR: [Synth 8-439] module '<hls IP submodule>' not found (xilinx.com)