Circuits---Sequential---Latches（3）

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最新推荐文章于 2024-09-27 21:53:49 发布

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文章标签： fpga开发笔记

本文链接：https://blog.csdn.net/pmlcreating/article/details/137098159

版权

本文介绍了多个基本的数字逻辑模块，包括多路选择器(Mux)、DFlip-Flops(DFF)、边沿检测电路以及双边缘触发器等，展示了它们在时钟控制下的工作原理和应用。

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1.Mux and DFF_1

只写一个子模块，别想复杂了

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);

    always@(posedge clk)
        begin      
            case(L)
                1'b0: Q<=q_in;
                1'b1: Q<=r_in;
            endcase        
        end
    
endmodule

2.Mux and DFF_2

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    
    wire p;
    always@(posedge clk)
        begin
            case(E)
                1'b0: p=Q;   //采用阻塞赋值
                1'b1: p=w;
            endcase
            
            case(L)
                1'b0: Q=p;
                1'b1: Q=R;
            endcase
            
        end

endmodule

3.DFFs and gates

module top_module (
    input clk,
    input x,
    output z
); 
    
    wire q1,q2,q3;
    always@(posedge clk)       
        begin          
            q1<=x^q1;
            q2<=x&(~q2);
            q3<=x|(~q3);          
        end
    assign z=~(q1|q2|q3);//不受时钟影响
endmodule

4.Create circuit from truth table

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
      
    always@(posedge clk)
       begin
           case({j,k})
               2'b00: Q<=Q;
               2'b01: Q<=0;
               2'b10: Q<=1;
               2'b11: Q<=~Q;
           endcase
       end
endmodule

5.Detect an edge

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    
    reg [7:0] p;
    always@(posedge clk)
        begin
           p<=in;
           pedge<=~p&in;  //原来为0，跳变为1后，输出位才为1.即~0&1=1
        end

    
endmodule

6.Detect both edges

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    
    reg [7:0] p;
    always@(posedge clk)
        begin
           p<=in;
           anyedge<=p^in;
        end

endmodule

7.Edge capture register

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);

    reg[31:0] p;
    
    always@(posedge clk)
        begin
           p<=in; 
        end
    
    always@(posedge clk)
        begin
            if(reset)
               out<=0;
             else
                 begin                   
                     out<=(p&~in)|out;  //捕获后，将一直保持1，只有复位才能置为0
                 end
            
        end
    
endmodule

8.Dual-edge triggered

module top_module (
    input clk,
    input d,
    output q
);

   reg p1,p2;
    always@(posedge clk)
        begin
           p1<=d; 
        end
    always@(negedge clk)
        begin
           p2<=d; 
        end
    assign q=clk ? p1 : p2;
    
endmodule