【HDLBits刷题】【Procedures】Always if

李十一11

已于 2022-04-07 21:08:23 修改

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分类专栏： HDLBits刷题 Verilog 文章标签： fpga开发

于 2022-04-07 21:07:17 首次发布

本文链接：https://blog.csdn.net/qq_22774445/article/details/124026394

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这篇博客介绍了如何使用Verilog语言实现一个2-to-1多路选择器。通过if语句和连续赋值两种方式展示了如何根据条件选择输出a或b。当sel_b1和sel_b2都为真时，选择b作为输出；否则选择a。示例代码中包含了两种实现方式的比较，并提供了相应的测试用例。

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An if statement usually creates a 2-to-1 multiplexer, selecting one input if the condition is true, and the other input if the condition is false.

always @(*) begin
    if (condition) begin
        out = x;
    end
    else begin
        out = y;
    end
end

This is equivalent to using a continuous assignment with a conditional operator:

assign out = (condition) ? x : y;

However, the procedural if statement provides a new way to make mistakes. The circuit is combinational only if out is always assigned a value.

A bit of practice

Build a 2-to-1 mux that chooses between a and b. Choose b if both sel_b1 and sel_b2 are true. Otherwise, choose a. Do the same twice, once using assign statements and once using a procedural if statement.

sel_b1	sel_b2	out_assign out_always
0	0	a
0	1	a
1	0	a
1	1	b

// synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    
    assign out_assign = (sel_b1 == 1 && sel_b2 == 1) ? b : a;
    always@(*)
        begin
            if(sel_b1 == 1 && sel_b2 == 1)
                out_always = b;
            else
                out_always = a;
        end
endmodule

还可以写成下面这样

// synthesis verilog_input_version verilog_2001
module top_module(
    input a,
    input b,
    input sel_b1,
    input sel_b2,
    output wire out_assign,
    output reg out_always   ); 
    assign out_assign = ({sel_b1,sel_b2} == 2'b11) ? b:a;
    always @(*)
        if ({sel_b1,sel_b2} == 2'b11)
            out_always = b;
        else out_always = a;
 
endmodule