Chipscope 工具调试和查看XILINX FPGA 内部的信号

top层代码如下；代码意义是运用IIC写入EEPROM 24LC04芯片，然后读取其值在数码管上显示

module lc04b_IIC(

	input clk,
	input rst_n,
	inout i2c_scl,
	inout i2c_sda,
	input key1,
	 output [5:0]     seg_sel,
    output [7:0]     seg_data
	
    );
	
localparam S_IDLE       = 0;
localparam S_READ       = 1;
localparam S_WAIT       = 2;
localparam S_WRITE      = 3;
reg[3:0] state;
reg [31:0] time_cnt;
reg  [7:0] read_data;
wire i2c_read_req_ack;
wire [7:0] i2c_read_data;
reg i2c_write_req;
reg i2c_read_req;

reg [7:0] i2c_slave_dev_addr;
reg [15:0] i2c_slave_reg_addr;
reg [7:0] i2c_write_data;
wire button_negedge;
ax_debounce ax_debounce_m0
(
    .clk             (clk),
    .rst             (~rst_n),
    .button_in       (key1),
    .button_posedge  (),
    .button_negedge  (button_negedge),
    .button_out      ()
);
wire[6:0] seg_data_0;
seg_decoder seg_decoder_m0(
    .bin_data  (read_data[3:0]),
    .seg_data  (seg_data_0)
);
wire[6:0] seg_data_1;
seg_decoder seg_decoder_m1(
    .bin_data  (read_data[7:4]),
    .seg_data  (seg_data_1)
);
seg_scan seg_scan_m0(
    .clk        (clk),
    .rst_n      (rst_n),
    .seg_sel    (seg_sel),
    .seg_data   (seg_data),
    .seg_data_0 ({1'b1,7'b1111_111}),
    .seg_data_1 ({1'b1,7'b1111_111}),
    .seg_data_2 ({1'b1,7'b1111_111}),
    .seg_data_3 ({1'b1,7'b1111_111}),
    .seg_data_4 ({1'b1,seg_data_1}),
    .seg_data_5 ({1'b1,seg_data_0})
);
always@(posedge clk or negedge rst_n)
	if(!rst_n)
	begin
	state<=S_IDLE;
	i2c_slave_dev_addr<=8'ha0;
	i2c_slave_reg_addr<=16'd0;
	i2c_read_req<=0;
	i2c_write_req<=0;
	time_cnt<=0;
	i2c_write_data<=0;
	read_data<=0;
	end
	else
	case(state)
	S_IDLE:
		if(time_cnt>=32'd12_499_999)
			state<=S_READ;
		else
			time_cnt<=time_cnt+1;
	S_READ:
		if(i2c_read_req_ack)
		begin
			read_data<=i2c_read_data;
			i2c_read_req<=0;
			state<=S_WAIT;	
		end
		else
		begin
			i2c_slave_dev_addr<=8'ha0;
			i2c_slave_reg_addr<=16'd0;
			i2c_read_req<=1;
		end

	S_WAIT:
		if(button_negedge)
		begin
		state<=S_WRITE;
		read_data<=read_data+8'd1;
		end
		
	S_WRITE:
		if(i2c_write_req_ack)
		begin
		i2c_write_req<=0;
		state<=S_READ;
		end
		else
		begin
		i2c_write_req<=1;
		i2c_write_data<=read_data;
		
		end
	default: state<=S_IDLE;
	endcase	
		

wire scl_padoen_o;
wire scl_pad_o;
assign i2c_scl=~scl_padoen_o?scl_pad_o:1'bz;
wire sda_padoen_o;
wire sda_pad_o;
assign i2c_sda=~sda_padoen_o?sda_pad_o:1'bz;
i2c_master_top i2c_master_top_inst
(
	.rst(~rst_n),
	.clk(clk),
	.clk_div_cnt(16'd500), //This register is used to prescale the SCL clock line. Due to the structure of the I2C
							       //interface, the core uses a 5*SCL clock internally. The prescale register must be
							       //programmed to this 5*SCL frequency (minus 1); 50Mhz/(5*100Khz) - 1 = 99;
							       //50Mhz/(5*400Khz) - 1 = 24;
	
	// I2C signals
	// i2c clock line
	.scl_pad_i(i2c_scl),                           // SCL-line input
	.scl_pad_o(scl_pad_o),                           // SCL-line output (always 1'b0)
	.scl_padoen_o(scl_padoen_o),                        // SCL-line output enable (active low)
	// i2c data line                            
	.sda_pad_i(i2c_sda),
	.sda_pad_o(sda_pad_o),                           // SDA-line output (always 1'b0)
	.sda_padoen_o(sda_padoen_o),                        // SDA-line output enable (active low)
	
	.i2c_addr_2byte(1'b0),                      // Is the register address 16bit?
	.i2c_read_req(i2c_read_req),                        // Read register request
	.i2c_read_req_ack(i2c_read_req_ack),                    // Read register request response
	.i2c_write_req(i2c_write_req),                       // Write register request
	.i2c_write_req_ack(i2c_write_req_ack),                   // Write register request response
	.i2c_slave_dev_addr(i2c_slave_dev_addr),              // I2c device address
	.i2c_slave_reg_addr(i2c_slave_reg_addr),             // I2c register address
	.i2c_write_data(i2c_write_data),                  // I2c write register data
	.i2c_read_data(i2c_read_data),              // I2c read register data
	.error()                            // The error indication, generally there is no response
);
wire [35:0] CONTROL0;
wire [255:0] TRIG0;
 chipscope_icon chipscope_icon_m0(
	.CONTROL0(CONTROL0));
chipscope_ila chipscope_ila_mo(
    .CONTROL(CONTROL0),
    .CLK(clk),
    .TRIG0(TRIG0)); 
	 
assign TRIG0[7:0]=i2c_write_data;
assign TRIG0[15:8]=i2c_read_data;
assign TRIG0[23:16]=read_data;
endmodule

Chipscope 工具调试操作如下

1.打开XILINX CORE GENERATOR 软件 新间工程在源代码工程下

2.生成如下两个IPcore

注意修改端口数核采样深度

![(https://img-blog.csdnimg.cn/20200721235418572.png?x-oss-process=image/watermark,type_ZmFuZ3poZW5naGVpdGk,shadow_10,text_aHR0cHM6Ly9ibG9nLmNzZG4ubmV0L3FxXzI0OTE3NDIx,size_16,color_FFFFFF,t_70)

3.生成的4个核文件导入到工程之中
4.在工程中实例IP并导出所要测试的数据，如下所示

wire [35:0] CONTROL0;
wire [255:0] TRIG0;

 chipscope_icon chipscope_icon_m0(
	.CONTROL0(CONTROL0));
	
chipscope_ila chipscope_ila_mo(
    .CONTROL(CONTROL0),
    .CLK(clk),
    .TRIG0(TRIG0)); 
	 
assign TRIG0[7:0]=i2c_write_data;
assign TRIG0[15:8]=i2c_read_data;
assign TRIG0[23:16]=read_data;

5.运行工程，将代码下入开发板中
6.运行分析软件，导入bit文件

7.建立分组

8.运行查看结果

结果一致，且能同时查看多个信号