实验代码
module mul_32(out,a,b);
input[31:0]a,b;output[63:0]out;
wire[63:0]out;
assign out=a*b;
endmodule
<span style="font-size:24px;">module mul_32(out,a,b);
input[31:0]a,b;
output[63:0]out;
wire[63:0]out;
assign out=a*b;
endmodule</span>
测试代码
<span style="font-size:24px;">`timescale 100ps/100ps
module mul_32_tb;
reg[31:0]a,b;
wire[63:0]out;
mul_32 uut(.a(a),
.b(b),
.out(out)
);
i