Verilog RTL 代码实战 09——纸上代码、心中电路

1.全加器

module test
(
	input		a,b,c_in,
	output		sum,c_out
);

assign sum = a ^ b ^ c_in;

assign c_out = (c_in & b)|(a & b)|(a & c_in);

endmodule

2.半加器

module test
(
input		a,b,
output    	c_out,sum
);

assign c_out = a & b;

assign sum   = a ^ b;

endmodule

3.四选一MUX

module test
(
	input		a,b,c,d,
	input [1:0]	sel,
	output reg	out
);

always@(*)begin
    case (sel)
	    2'b00: out = a;
	    2'b01: out = b;
        2'b10: out = c;
	    2'b11: out = d;
	  default: out = a;
    endcase
end

endmodule

4.10分频

module test
(
	input		clk,
	input		rst_n,
	output reg 	clk_div
);
//参数
parameter N = 10;

//内部信号
reg [3:0]	cnt;

//功能块
always@(posedge clk or negedge rst_n)begin
	if (!rst_n)begin
		cnt <= 0;
	end
	else if(cnt == N - 1 ) begin
		cnt <= 0;
	end
	else begin
		cnt <= cnt + 1;
	end
end

always@(posedge clk or negedge rst_n)begin
	if (!rst_n) begin
		clk_div <= 0;
	end
	else if (cnt <= (N/2)-1) begin
		clk_div <= 1;
	end
	else begin
		clk_div <= 0;
	end
end

endmodule

5.3分频

module test
(
	input		clk,
	input		rst_n,
	output wire	clk_div
);

//参数
parameter		N = 2'd1;	
//内部信号
reg [2:0]		cnt_pose;
reg [2:0]		cnt_nege;
reg			clk_pose;
reg			clk_nege;
//功能块
always@(posedge clk or negedge rst_n)begin     // 对上升沿计数
	if(!rst_n)
		cnt_pose <= 0;
	else if(cnt_pose == 2*N)
		cnt_pose <= 0;
	else
		cnt_pose <= cnt_pose + 1;
end

always@(posedge clk or negedge rst_n)begin  // 中间时钟clk_pose
	if(!rst_n)
		clk_pose<=0;
	else if(cnt_pose == N||cnt_pose == 2*N)
		clk_pose <= ~clk_pose;
	else
		clk_pose <= clk_pose;
end

always@(negedge clk or negedge rst_n)begin     // 对下降沿计数
	if(!rst_n)
		cnt_nege <= 0;
	else if(cnt_nege == 2*N)
		cnt_nege <= 0;
	else
		cnt_nege <= cnt_nege + 1;
end

always@(negedge clk or negedge rst_n)begin  // 中间时钟clk_nege
	if(!rst_n)
		clk_nege <= 0;
	else if(cnt_nege == N||cnt_nege == 2*N)
		clk_nege <= ~clk_nege;
	else
		clk_nege <= clk_nege;
end
	
assign clk_div = clk_pose|clk_nege;		   // 2N+1分频时钟输出

endmodule

6.移位寄存器的序列检测器

module test
(
	input		clk,
	input		rst_n,
	input		x,
	output wire	z
);

reg [4:0]	shift;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		shift <= 0;
	else
		shift <= {shift[3:0],x};
end

assign z = (shift == 5'b10010)?1:0;

endmodule

7.状态机的序列检测器

	module test
	(
	    input           clk,
	    input           rst_n,
	    input           x,
	    output wire     z
	);
	
	//参数  
	//状态机设置采用独热码
	localparam      IDLE =8'b0000_0001;
	localparam      A    =8'b0000_0010;
	localparam      B    =8'b0000_0100;
	localparam      C    =8'b0000_1000;
	localparam      D    =8'b0001_0000;
	localparam      E    =8'b0010_0000;
	localparam      F    =8'b0100_0000;
	localparam      G    =8'b1000_0000;
	
	//内部信号
	reg [7:0]   state;
	
	//功能
	//状态机
	always  @(posedge clk or negedge rst_n)begin
	    if(rst_n==1'b0)begin
	        state <= IDLE;
	    end
	    else 
	        case(state)
	                IDLE:if(x==1)
	                        state <= A;
	                     else
	                        state <= IDLE;
	                    A:if(x==0)
	                        state <= B;
	                     else
	                        state <= A;
	                    B:if(x==0)
	                        state <= C;
	                     else
	                        state <= F;
	                    C:if(x==1)
	                        state <= D;
	                     else
	                        state <= G;
	                    D:if(x==0)
	                        state <= E;
	                     else
	                        state <= A;
	                    E:if(x==1)
	                        state <= A;
	                     else
	                        state <= C;
	                    F:if(x==0)
	                        state <= B;
	                     else
	                        state <= A;
	                    G:if(x==1)
	                        state <= F;
	                     else
	                        state <= IDLE;
	              default:  state <= IDLE;
	        endcase
	    end
	    
	//检测到10010给z拉高
	assign z = (state==D && x==0)? 1 : 0;
	
	endmodule

8.监沿器

module test
(
	input		clk,
	input		rst_n,
	input		signal,
	output wire	pose,
	output wire	nege
);
//内部信号
reg		signal_before;
//前一刻信号值寄存
always @(posedge clk or negedge rst_n)begin
 	 if(rst_n==1'b0)begin
	 signal_before <= 0;
	 end
	 else begin
	 signal_before <= signal ;
	 end
end
//上升下降判断
assign nege = signal==0 && signal_before==1;
assign pose = signal==1 && signal_before==0;


endmodule

9.PWM输出

module test
(
	input		clk,
	input		rst_n,
	output reg	pwm
);
//参数 周期以及占空比
parameter	CYCLE   = 50;  //1000ns = 1us
parameter	PERCENT = 20;  //20%

reg [7:0]	cnt_T;		//随计数最大值改动，这里最大计数到49，因此需要8位

//功能块
always@(posedge clk or negedge rst_n)begin
	if (!rst_n)
		cnt_T <= 0;
	else if(cnt_T == CYCLE-1)
		cnt_T <= 0;
	else
		cnt_T <= cnt_T +1;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		pwm <= 0;
	else if (cnt_T <= CYCLE * PERCENT /100 -1 )
		pwm <= 1;
	else
		pwm <= 0;
end

endmodule