HDLbits Count clock

HDLbits Count clock

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.

可以分为三个部分，时（12），分秒（60），pm，用bcd计数器计算分秒。

需要注意的点：

1.小时默认值为8‘h12，并且没有0时，12时结束后直接为1时

2.pm只有在11:59:59到12:00：00翻转

3.count60模块需要注意高4位ena的赋值，对秒来说第一条判断语句没有影响，对于分来说会出错

assign ena0=(d[3:0]==4'd9)?1:0;//打咩
assign ena0=(ena&&(d[3:0]==4'd9))?1:0;//可以

所有代码：

module bcdcount(
	input clk,
    input reset,
    input ena,
    output [3:0] d
);
    parameter [3:0] CARRY;  //进位值
    parameter [3:0] DEF;	//默认值
    always @(posedge clk) begin
        if(reset) d<=DEF;
        else if(ena) begin
            if(d==CARRY) d<=DEF;
            else d<=d+4'b1;
        end
        else d<=d;
    end
endmodule

module count_60(
	input clk,
    input reset,
    input ena,
    output [7:0] d
);
    wire ena0;
    assign ena0=(ena&&(d[3:0]==4'd9))?1:0;
    bcdcount #(4'd9,4'd0) bcdcnt0(clk,reset,ena,d[3:0]);
    bcdcount #(4'd5,4'd0) bcdcnt1(clk,reset,ena0,d[7:4]);
endmodule

module count_hh(
	input clk,
    input reset,
    input ena,
    output [7:0] d
);
    always @(posedge clk) begin
        if(reset) d<=8'h12;	//默认值12
        else if(ena) begin
            if(d[7:4]==4'h0) begin
                if(d[3:0]==4'h9) d<=8'h10;
            	else d<={d[7:4],d[3:0]+4'h1};
        	end
            else if(d[7:4]==4'h1) begin
                if(d[3:0]==4'h2) d<=8'h1;
                else d<={d[7:4],d[3:0]+4'h1};
            end
        end
    end
endmodule

module top_module(
    input clk,
    input reset,
    input ena,
    output pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 

    wire ena_m，ena_h;
    reg pm_o;
    assign ena_m=(ss==8'h59)?1:0;
    assign ena_h=(mm==8'h59&&ss==8'h59)?1:0;
    count_60 cnt60_s(clk,reset,ena,ss);
    count_60 cnt60_m(clk,reset,ena_m,mm);
    count_hh cnt_h(clk,reset,ena_h,hh);
	
    always @(posedge clk) begin
        if(reset) pm_o<=1'b0;
        else if(hh==8'h11&&mm==8'h59&&ss==8'h59) pm_o<=~pm_o;
        else pm_o<=pm_o;
    end
    assign pm=pm_o;
endmodule