[FPGA]VGA驱动模块

module VGAdriver(
	input			clk,
	input			rst,
	output			vgaHS,
	output			vgaVS,
	output	[15:0]	vgaRGB,
	input	[15:0]	pixelValue,
	output	[9:0]	pixelXPos,
	output	[9:0]	pixelYPos
);

	parameter Hsync = 10'd96;
	parameter Hback = 10'd48;
	parameter Hdisp = 10'd640;
	parameter Hfront = 10'd16;
	parameter Htotal = 10'd800;

	parameter Vsync = 10'd2;
	parameter Vback = 10'd33;
	parameter Vdisp = 10'd480;
	parameter Vfront = 10'd10;
    parameter Vtotal = 10'd525;

	reg [9:0] Hcount, Vcount;
	always @(posedge clk or negedge rst) begin
		if(!rst) begin
			Hcount <= 10'b0;
			Vcount <= 10'b0;
		end
		else if(Hcount == Htotal) begin
			Hcount <= 10'b0;
			if(Vcount == Vtotal) begin
				Vcount <= 10'b0;
			end
			else begin
				Vcount <= Vcount + 1'b1;
			end
		end
		else begin
			Hcount <= Hcount + 1'b1;
		end
	end
	
	assign vgaHS = Hcount < Hsync ? 1'b0 : 1'b1;
	assign vgaVS = Vcount < Vsync ? 1'b0 : 1'b1;

	assign vgaEN = (Hcount >= Hsync + Hback) && (Hcount < Hsync + Hback + Hdisp) &&
					(Vcount >= Vsync + Vback) && (Vcount < Vsync + Vback + Vdisp) ?
					1'b1 : 1'b0;
	assign vgaRGB = vgaEN ? pixelValue : 16'b0;

	assign vgaREQ = (Hcount >= Hsync + Hback - 1'b1) && (Hcount < Hsync + Hback + Hdisp - 1'b1) &&
					(Vcount >= Vsync + Vback - 1'b1) && (Vcount < Vsync + Vback + Vdisp - 1'b1) ?
					1'b1 : 1'b0;
	assign pixelXPos = vgaREQ ? Hcount - (Hsync + Hback - 1'b1) : 10'b0;
	assign pixelYPos = vgaREQ ? Vcount - (Vsync + Vback - 1'b1) : 10'b0;

endmodule