前言
该博客为本人做HDLBits习题时的心得记录总结,欢迎大家一起交流进步。
Verilog Language
Circuits
Combinational Logic
Sequential Logic
Latches and Flip-Flops
Counters
Shift Registers
More Circuits
Finite State Machines
Simple FSM 1—Simple state transitions 3
Simple one-hot state transitions 3—Design a Moore FSM
One-hot FSM—PS/2 packet parser and datapath
Serial receiver—Serial receiver with parity checking