使用VDHL语言编写Testbench

使用库声明

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

use std.textio.all;-- testio程序包是std库的一部分
use ieee.std_logic_textio.all;

时钟复位生成

constant clk_period : time := 25 ns;

-- 时钟控制
F_clk_40mhz_process :process
   begin
		F_clk_40mhz <= '0';
		wait for clk_period/2;
		F_clk_40mhz <= '1';
		wait for clk_period/2;
   end process;

-- 复位控制
F_rst_n_process :process
   begin
		F_rst_n <= '0';
		wait for clk_period*200;
		F_rst_n <= '1';
		wait;
   end process;

过流信号滤波功能测试，设置输入的过流信号oc，

-- 电源控制模块 
cmos_oc_process :process
begin
	cmos_11v_oc  <= '1';
	cmos_3v3_oc  <= '1';
	cmos_1v8_oc  <= '1';
    wait for 10ms;

	cmos_11v_oc  <= '0';
	cmos_3v3_oc  <= '1';
	cmos_1v8_oc  <= '1';
	wait for 1ms;-- 1ms的过流信号，用来体现出2ms的滤波

	cmos_11v_oc  <= '1';
	cmos_3v3_oc  <= '1';
	cmos_1v8_oc  <= '1';
	wait for 10ms;

	cmos_11v_oc  <= '0';
	cmos_3v3_oc  <= '1';
	cmos_1v8_oc  <= '1';
	wait for 3ms;-- 2.25ms的过流信号

	cmos_11v_oc  <= '1';
	cmos_3v3_oc  <= '1';
	cmos_1v8_oc  <= '1';	
	wait ;

end process;

SRAM读测试，从TXT文本中读出图像数据，用于图像处理

--SRAM输入挡板数据
sram_process_2 :process(clk,rst)
	file file_in : text;
	variable line_in : line;
	variable data_in : std_logic_vector(13 downto 0);  
begin
	if rst='1' then
		sram_rddata<=(others=>'0');
	elsif clk'event and clk='1' then
		if cmos_state=x"3" and cmos_cmd_rx_sh=cmd_vs then
			file_open(file_in,"e:\forsim\db_img.txt",read_mode);--从文件中读取挡板数据
			sram_rddata<=(others=>'0');

		elsif sram_ncs(0)='0' and d1_sram_ncs(0)='1' and sram_noe='0' and d1_sram_noe='1' and sram_addr>=180000 and sram_addr<360000 then
			readline(file_in,line_in);
			read(line_in,data_in);			
			sram_rddata(31 downto 16)<="00"&data_in;

			readline(file_in,line_in);
			read(line_in,data_in);			
			sram_rddata(15 downto 0)<="00"&data_in;	
		
		elsif cmos_state=x"9" and row_cnt=521 and column_cnt=652 then
			file_close(file_in);
			sram_rddata<=(others=>'0');
		end if;
	end if;
end process;

串口通信测试，设置串口接收信号uart_rx

	-- 地检数据生成   
	uart_rx_process :process
	begin
		uart_rx <='1';
		trans_byte <= (others=>'0');
		trans_data <= (others=>'0');		
		wait for 200ms;		
		for i in 3 downto 0 loop -- 连续发送4个2A
			trans_byte <= x"2A";
			wait until rising_edge(clk);
			trans_data <= '1' & trans_byte & '0';
			wait until rising_edge(clk);
			
			for j in 0 to 9 loop
				uart_rx <=trans_data(j);
				wait for clk_period_56mhz*486;
			end loop;
			uart_rx <='1';
			wait for clk_period_56mhz*1000;
		end loop;
		
		trans_byte <= x"00";
		wait until rising_edge(clk);
		for i in 179 downto 0 loop -- 180个字节
			trans_data <= '1' & trans_byte & '0';
			wait until rising_edge(clk);
		
			for j in 0 to 9 loop
				uart_rx <=trans_data(j);
				wait for clk_period_56mhz*486;
			end loop;
			uart_rx <='1';
			wait for clk_period_56mhz*1000;

			trans_byte <= trans_byte+'1';
			wait until rising_edge(clk);			
		end loop;
		
		wait ;
	end process;