hdl答案:Always（ case2、 casez、 nolatches）、Conditional、Reduction、Gates100、Vector100r、Popcount255

Always case2

A priority encoder is a combinational circuit that, when given an input bit vector, outputs the position of the first 1 bit in the vector. For example, a 8-bit priority encoder given the input 8'b10010000 would output 3'd4, because bit[4] is first bit that is high.

Build a 4-bit priority encoder. For this problem, if none of the input bits are high (i.e., input is zero), output zero. Note that a 4-bit number has 16 possible combinations.

使用case(in）要报错，但是使用casez就可以。

// synthesis verilog_input_version verilog_2001
module top_module (
    input [3:0] in,
    output reg [1:0] pos  );
always@(*)begin
	casez (in) 
        4'b??10:      pos = 2'd1; 
        4'b?100:      pos = 2'd2; 
        4'b1000:      pos = 2'd3; 
        default :     pos = 0; 
	endcase
end
endmodule

Always casez

Build a priority encoder for 8-bit inputs. Given an 8-bit vector, the output should report the first bit in the vector that is 1. Report zero if the input vector has no bits that are high. For example, the input 8'b10010000 should output 3'd4, because bit[4] is first bit that is high.

和上面的题其实是一样，就是换换数据位宽的事儿。

// synthesis verilog_input_version verilog_2001
module top_module (
    input [7:0] in,
    output reg [2:0] pos  );
always@(*)begin
	casez (in) 
        8'b??????10:      pos = 3'd1; 
        8'b?????100:      pos = 3'd2; 
        8'b????1000:      pos = 3'd3; 
        8'b???10000:      pos = 3'd4; 
        8'b??100000:      pos = 3'd5; 
        8'b?1000000:      pos = 3'd6; 
        8'b10000000:      pos = 3'd7; 		
        default :     	  pos = 3'd0; 
	endcase
end
endmodule

Always nolatches

Suppose you're building a circuit to process scancodes from a PS/2 keyboard for a game. Given the last two bytes of scancodes received, you need to indicate whether one of the arrow keys on the keyboard have been pressed. This involves a fairly simple mapping, which can be implemented as a case statement (or if-elseif) with four cases.

// synthesis verilog_input_version verilog_2001
module top_module (
    input [15:0] scancode,
    output reg left,
    output reg down,
    output reg right,
    output reg up  ); 
always@(*)begin
    		left=0;
			down=0;
			right=0;
			up=0;
	case(scancode)
		16'he06b:	left=1;
		16'he072:	down=1;
		16'he074:	right=1;
		16'he075:	up=1;
		default:begin 
					left=0;
					down=0;
					right=0;
					up=0;
		end 
	endcase
end
endmodule

Conditional

A Bit of Practice

Given four unsigned numbers, find the minimum. Unsigned numbers can be compared with standard comparison operators (a < b). Use the conditional operator to make two-way min circuits, then compose a few of them to create a 4-way min circuit. You'll probably want some wire vectors for the intermediate results.

module top_module (
    input [7:0] a, b, c, d,
    output [7:0] min);
	wire [7:0]med1,med2;
    assign med1 = a<b? a: b;
    assign med2 = c<d? c: d;
	assign min = med1<med2? med1: med2;
endmodule

Reduction

A Bit of Practice

Parity checking is often used as a simple method of detecting errors when transmitting data through an imperfect channel. Create a circuit that will compute a parity bit for a 8-bit byte (which will add a 9th bit to the byte). We will use "even" parity, where the parity bit is just the XOR of all 8 data bits.

module top_module (
    input [7:0] in,
    output parity); 
assign	parity=^in;
endmodule

Gates100

Build a combinational circuit with 100 inputs, in[99:0].

There are 3 outputs:

• out_and: output of a 100-input AND gate.
• out_or: output of a 100-input OR gate.
• out_xor: output of a 100-input XOR gate.

  module top_module( 
      input [99:0] in,
      output out_and,
      output out_or,
      output out_xor 
  );
  	assign out_and=∈
  	assign out_or=|in;
  	assign out_xor=^in;
  endmodule

  Vector100r

Given a 100-bit input vector [99:0], reverse its bit ordering.

module top_module( 
    input [99:0] in,
    output [99:0] out
);
integer i;
always@(*)begin
    for(i = 0; i <= 99; i = i + 1)begin 
		out[i]=in[99-i];
	end 
end
endmodule

Popcount255

A "population count" circuit counts the number of '1's in an input vector. Build a population count circuit for a 255-bit input vector.

module top_module( 
    input [254:0] in,
    output [7:0] out );
	integer i;
always@(*)begin 
	out=0;
	for(i = 0; i <= 254; i = i + 1)begin 
		if(in[i]==1'b1)
			out=out+8'd1;
		else 
			out=out;
	end 
end 
endmodule

可以理解为，for循环是在一瞬间就完成的，不需要耗费时间，组合逻辑。