HDLBits-Verilog Language-Modules:Hierarchy(模块：层次结构)

目录

Module shift8

---

Module shift8

This exercise is an extension of module_shift. Instead of module ports being only single pins, we now have modules with vectors as ports, to which you will attach wire vectors instead of plain wires. Like everywhere else in Verilog, the vector length of the port does not have to match the wire connecting to it, but this will cause zero-padding or trucation of the vector. This exercise does not use connections with mismatched vector lengths.

You are given a module my_dff8 with two inputs and one output (that implements a set of 8 D flip-flops). Instantiate three of them, then chain them together to make a 8-bit wide shift register of length 3. In addition, create a 4-to-1 multiplexer (not provided) that chooses what to output depending on sel[1:0]: The value at the input d, after the first, after the second, or after the third D flip-flop. (Essentially, sel selects how many cycles to delay the input, from zero to three clock cycles.)

The module provided to you is: module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

The multiplexer is not provided. One possible way to write one is inside an always block with a case statement inside. (See also: mux9to1v)

本练习是module_shift的扩展. 模块端口不再只是单个引脚，我们现在有带有矢量作为端口的模块，您将在其上连接线矢量而不是普通线。与 Verilog 中的其他任何地方一样，端口的向量长度不必与连接到它的电线匹配，但这会导致向量的零填充或截断。本练习不使用矢量长度不匹配的连接。

您将获得一个my_dff8具有两个输入和一个输出的模块（实现一组 8 个 D 触发器）。实例化其中的三个，然后将它们链接在一起以形成一个长度为 3 的 8 位宽移位寄存器。此外，创建一个 4 对 1 多路复用器（未提供），根据以下条件选择输出内容sel[1:0]： 输入值d，在第一个之后，在第二个之后，或者在第三个 D 触发器之后。（本质上，sel选择延迟输入的周期数，从零到三个时钟周期。）

提供给您的模块是： module my_dff8 ( input clk, input [7:0] d, output [7:0] q );

不提供多路复用器。一种可能的写法是在always一个case语句块中。（另见：mux9to1v)

module top_module ( 
    input clk, 
    input [7:0] d, 
    input [1:0] sel, 
    output [7:0] q 
);
    wire [7:0] q1,q2,q3;
    my_dff8 U1( clk, d, q1 );
    my_dff8 U2( clk,q1, q2 );
    my_dff8 U3( clk,q2, q3 );
    always@(*)
        begin
            case(sel)
                2'd0: q <= d;
                2'd1: q <= q1;
                2'd2: q <= q2;
                2'd3: q <= q3;
            endcase
        end
endmodule