ram 不同时钟读写（仿真已过，没试过板子）

ram 先进，后出，，，（进出对象是ram）

进入有使能信号控制读入长度，本代码为工程代码其中之一。ram 输入位宽是8位，输出虽然也是8位但是进行了分频，模块输出位宽是一位。

`timescale 1ns / 1ps
//

//


module ram_operate(
input                clk1,//40
input                clk2,//64
input                rst,
input                en,
input    [31:0]      len,
input    [7:0]       din,
output        data_out
);

reg [7:0]   buf_din;
reg [10:0]  addra;
reg [10:0]  addrb;
//reg  enb;

reg [31:0] cnt_in_ram;
reg [31:0] cnt_out_ram;

reg  buf_in_en ;
reg  buf_out_en;
//reg   flag;


//==================初始状态========输入使能======================
always @(posedge clk1 or negedge rst)begin 
	if(!rst) buf_in_en <= 0;
	else if(en) buf_in_en<= 1;
	else if(cnt_in_ram == len) buf_in_en <= 0;
	else  buf_in_en <= 0;
end
//===================================输出使能============
always @(posedge clk2 or negedge rst)begin 
	if(!rst) buf_out_en <= 0;
	else if( cnt_out_ram == len) buf_out_en <= 0;
	else if(cnt_in_ram == len) begin 
	       buf_out_en <= 'd1;       
	end
end
//===================数据读入=============================
always @(posedge clk1 or negedge rst) begin //40
    buf_din<=  din;
    if(!rst)begin 
        cnt_in_ram <= 0;
        addra  <= 0;
    end
    else if(buf_in_en)begin
            if(cnt_in_ram == len)begin 
                cnt_in_ram <= 0;
                addra  <= 0;
            end
            else begin 
               cnt_in_ram <= cnt_in_ram + 'd1;
               addra  <= addra + 'd1;
            end
     end
    else begin 
          cnt_in_ram <= 0;
          addra  <= 0;
    end
end
// ===================数据读取==========================
reg [9:0] cnt;
always @(posedge clk2 or negedge rst) begin 
    if(!rst)begin 
        cnt <= 0;
    end
    else if(buf_out_en)begin
        if(cnt == 'd500) begin 
            cnt<= 0;
        end
        else begin
             cnt <= cnt + 'd1 ;
        end
    end
end

always @(posedge clk2 or negedge rst) begin 
    if(!rst)begin 
        cnt_out_ram <= 0;
        addrb  <= 0;
    end
    else if(buf_out_en)begin
        if(cnt_out_ram == len)begin 
            cnt_out_ram <= 0;
            addrb  <= 0;
        end
//==============================================================
        else begin
           if(cnt == 'd500)begin 
               cnt_out_ram <= cnt_out_ram + 'd1;
               addrb  <= addrb + 'd1;
           end
           else begin 
               cnt_out_ram <= cnt_out_ram ;
               addrb  <= addrb ;  
           end

        end
//===========================================================
    end
    else begin 
          cnt_out_ram <= 0;
          addrb  <= 0;
    end
end
//=================================================
wire [7:0] dout ;
blk_mem_gen_0 in_out_ram(
.clka(clk1),
.wea(buf_in_en),
.addra(addra),
.dina(buf_din),
.clkb(clk2),
.enb(buf_out_en),
.addrb(addrb),
.doutb(dout)
 );
//======================分频==============================
reg d;
always @(posedge clk2 or negedge rst) begin 
    if(!rst)begin 
        d <= 0;
    end
    else if(buf_out_en)begin
        if(cnt >'d0 && cnt <= 'd62) begin 
           d <=dout[7];
        end
        else if((cnt >= 'd63 && cnt <= 'd120))begin
             d <=dout[6];
        end
        else if((cnt >= 'd121 && cnt <= 'd180))begin
             d <=dout[5];
        end
        else if((cnt >= 'd181 && cnt <= 'd250))begin
             d <=dout[4];
        end
        else if((cnt >= 'd251 && cnt <= 'd310))begin
             d <=dout[3];
        end
        else if((cnt >= 'd311 && cnt <= 'd370))begin
             d <=dout[2];
        end
        else if((cnt >= 'd371&& cnt <= 'd440))begin
             d <=dout[1];
        end
         else if((cnt >= 'd372&& cnt <='d500))begin
             d <=dout[0];
        end
        else begin 
            d <='d0;
        end
    end
end
assign data_out = d;
//==============================================
endmodule

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2022/10/19 19:31:13
// Design Name: 
// Module Name: test_top_tb
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module tb_ram_operater();
reg         clk1;
reg         clk2;
reg         en;
reg [7:0]   d;
reg         rst_n;
reg [31:0]  len;
wire [7:0]  q;
initial begin
	        clk1 <= 0;          clk2 <= 0;    en <= 0;
	        rst_n <= 0;         len <= 31'd6;
	#25;    rst_n = 1;         
end
always #12.5   clk1 = ~clk1;
always #8      clk2 = ~clk2;

initial begin
    #1000 
            en <= 'd1;
	        d <= 8'b10011010;
	#25;    d <= 8'b01101100;
	#25;    d <= 8'b10101011;
	#25;    d <= 8'b11101011;
	#25;    d <= 8'b11110110;
	#25;    d <= 8'b11111111;      
	#25;    d <= 'd0;               en <= 0;
end

initial begin
    #4000      
               en <= 'd1;  
	           d <= 8'b10011010;
	#25;       d <= 8'b01101100;
	#25;       d <= 8'b10101011;
	#25;       d <= 8'b11101011;
	#25;       d <= 8'b11110110;
	#25;       d <= 8'b11111111;
	#25;         d <= 'd0;           en <=0;    
end

initial begin
    #8000      en <= 'd1;
	           d <= 8'b10011010;
	#25;       d <= 8'b01101100;
	#25;       d <= 8'b10101011;
	#25;       d <= 8'b11101011;
	#25;       d <= 8'b11110110;
	#25;       d <= 8'b11111111;
	#25;       d <= 'd0;           en <=0;    
end

ram_operate ram_operater_test(
.clk1(clk1),//40
.clk2(clk2),//64
.rst(rst_n),
.en(en),
.len(len),
.din(d),
.dout(q)
);
endmodule