【verilog_7】: 设计一个 32 位 ALU 支持加法、减法、与、或、异或、取非这六中运算

设计一个 32 位 ALU 支持加法、减法、与、或、异或、取非这六中运算

author : Mr.Mao
e-mail : 2458682080@qq.com

module ALU_32(
	input [31:0] data_a_in,
	input [31:0] data_b_in,
	input carry_in,
	input [3:0] op_code,
	output reg carry_out,
	output reg [31:0] result_out
);

	localparam	ADD = 0, SUB = 1, AND = 2, OR = 3, XOR = 4, NONA = 5, NONB = 6;
	
	always @ (op_code or data_a_in or data_b_in)
		case(op_code)
			ADD	:	{carry_out,result_out} <= data_a_in + data_b_in + carry_in;
			SUB	:	{carry_out,result_out} <= {data_a_in[31],data_a_in} - {data_b_in[31],data_b_in} - carry_in;
			AND	:	result_out <= data_a_in & data_b_in;
			OR		:	result_out <= data_a_in | data_b_in;			
			XOR	:	result_out <= data_a_in ^ data_b_in;
			NONA	:	result_out <= ~data_a_in;
			NONB	:	result_out <= ~data_b_in;
			default	:	result_out <= data_a_in;
		endcase

endmodule