出现报错Object reference not set to an instance of an object

情况描述:

我在Unity的Hierarchy最初始的Main Camera进行挂载了一个脚本,后来因为其他原因,删除了最初始的Main Camera,而后新建了一个Camera,并命名为Main Camera,然后挂载了之前相同的脚本之后,发现会出现下列bug:Object reference not set to an instance of an object。

原因:

未将对象引用到对象的实例.也就是没有实例化一个对象。当声明了变量,但是没有赋值,仍然为null.用的时候就会报错。

解决方法:

点击选中新建Camera,在Inspector属性设置中,找到tag下拉菜单中的Main Camera选中。重新运行程序,报错消除!

 

 

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Table of Contents Section 1 Introduction to SystemVerilog ...................................................................................................... 1 Section 2 Literal Values.................................................................................................................................. 4 2.1 Introduction (informative) ...............................................................................................................4 2.2 Literal value syntax..........................................................................................................................4 2.3 Integer and logic literals ..................................................................................................................4 2.4 Real literals ......................................................................................................................................5 2.5 Time literals .....................................................................................................................................5 2.6 String literals....................................................................................................................................5 2.7 Array literals ....................................................................................................................................6 2.8 Structure literals ...............................................................................................................................6 Section 3 Data Types....................................................................................................................................... 8 3.1 Introduction (informative) ...............................................................................................................8 3.2 Data type syntax...............................................................................................................................9 3.3 Integer data types ...........................................................................................................................10 3.4 Real and shortreal data types .........................................................................................................11 3.5 Void data type ................................................................................................................................11 3.6 chandle data type ...........................................................................................................................11 3.7 String data type ..............................................................................................................................12 3.8 Event data type...............................................................................................................................16 3.9 User-defined types .........................................................................................................................16 3.10 Enumerations .................................................................................................................................17 3.11 Structures and unions.....................................................................................................................22 3.12 Class...............................................................................................................................................26 3.13 Singular and aggregate types .........................................................................................................27 3.14 Casting ...........................................................................................................................................27 3.15 $cast dynamic casting ....................................................................................................................28 3.16 Bit-stream casting ..........................................................................................................................29 Section 4 Arrays ............................................................................................................................................ 32 4.1 Introduction (informative) .............................................................................................................32 4.2 Packed and unpacked arrays ..........................................................................................................32 4.3 Multiple dimensions ......................................................................................................................33 4.4 Indexing and slicing of arrays........................................................................................................34 4.5 Array querying functions ...............................................................................................................35 4.6 Dynamic arrays ..............................................................................................................................35 4.7 Array assignment ...........................................................................................................................37 4.8 Arrays as arguments.......................................................................................................................38 4.9 Associative arrays ..........................................................................................................................39 4.10 Associative array methods .............................................................................................................41 4.11 Associative array assignment.........................................................................................................44 4.12 Associative array arguments ..........................................................................................................44 4.13 Associative array literals................................................................................................................44 4.14 Queues ...........................................................................................................................................45 4.15 Array manipulation methods .........................................................................................................47 Section 5 Data Declarations ......................................................................................................................... 52 5.1 Introduction (informative) .............................................................................................................52 5.2 Data declaration syntax..................................................................................................................52 5.3 Constants........................................................................................................................................52 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 viii Copyright 2004 Accellera. All rights reserved . 5.4 Variables ........................................................................................................................................53 5.5 Scope and lifetime .........................................................................................................................54 5.6 Nets, regs, and logic.......................................................................................................................55 5.7 Signal aliasing................................................................................................................................56 5.8 Type compatibility .........................................................................................................................58 Section 6 Attributes....................................................................................................................................... 61 6.1 Introduction (informative) .............................................................................................................61 6.2 Default attribute type .....................................................................................................................61 Section 7 Operators and Expressions.......................................................................................................... 62 7.1 Introduction (informative) .............................................................................................................62 7.2 Operator syntax..............................................................................................................................62 7.3 Assignment operators ....................................................................................................................62 7.4 Operations on logic and bit types ..................................................................................................63 7.5 Wild equality and wild inequality..................................................................................................63 7.6 Real operators ................................................................................................................................64 7.7 Size.................................................................................................................................................64 7.8 Sign ................................................................................................................................................64 7.9 Operator precedence and associativity ..........................................................................................64 7.10 Built-in methods ............................................................................................................................65 7.11 Static Prefixes ................................................................................................................................66 7.12 Concatenation ................................................................................................................................67 7.13 Unpacked array expressions ..........................................................................................................67 7.14 Structure expressions .....................................................................................................................68 7.15 Tagged union expressions and member access..............................................................................70 7.16 Aggregate expressions ...................................................................................................................71 7.17 Operator overloading .....................................................................................................................72 7.18 Streaming operators (pack / unpack) .............................................................................................73 7.19 Conditional operator ......................................................................................................................77 7.20 Set membership..............................................................................................................................77 Section 8 Procedural Statements and Control Flow.................................................................................. 79 8.1 Introduction (informative) .............................................................................................................79 8.2 Statements ......................................................................................................................................79 8.3 Blocking and nonblocking assignments ........................................................................................80 8.4 Selection statements.......................................................................................................................81 8.5 Loop statements .............................................................................................................................87 8.6 Jump statements.............................................................................................................................89 8.7 Final blocks....................................................................................................................................89 8.8 Named blocks and statement labels ...............................................................................................90 8.9 Disable ...........................................................................................................................................90 8.10 Event control..................................................................................................................................91 8.11 Level-sensitive sequence controls .................................................................................................93 8.12 Procedural assign and deassign removal .......................................................................................94 Section 9 Processes........................................................................................................................................ 95 9.1 Introduction (informative) .............................................................................................................95 9.2 Combinational logic.......................................................................................................................95 9.3 Latched logic..................................................................................................................................96 9.4 Sequential logic..............................................................................................................................96 9.5 Continuous assignments ................................................................................................................96 9.6 fork...join........................................................................................................................................97 9.7 Process execution threads ..............................................................................................................98 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. ix 9.8 Process control ...............................................................................................................................98 9.9 Fine-grain process control ...........................................................................................................100 Section 10 Tasks and Functions................................................................................................................... 102 10.1 Introduction (informative) ...........................................................................................................102 10.2 Tasks ............................................................................................................................................103 10.3 Functions......................................................................................................................................104 10.4 Task and function argument passing ...........................................................................................106 10.5 Import and export functions.........................................................................................................109 Section 11 Classes.......................................................................................................................................... 111 11.1 Introduction (informative) ...........................................................................................................111 11.2 Syntax ..........................................................................................................................................112 11.3 Overview......................................................................................................................................113 11.4 Objects (class instance)................................................................................................................113 11.5 Object properties..........................................................................................................................114 11.6 Object methods ............................................................................................................................114 11.7 Constructors .................................................................................................................................115 11.8 Static class properties...................................................................................................................116 11.9 Static methods..............................................................................................................................116 11.10 This ..............................................................................................................................................116 11.11 Assignment, re-naming and copying ...........................................................................................117 11.12 Inheritance and subclasses ...........................................................................................................118 11.13 Overridden members....................................................................................................................119 11.14 Super ............................................................................................................................................119 11.15 Casting .........................................................................................................................................120 11.16 Chaining constructors ..................................................................................................................120 11.17 Data hiding and encapsulation .....................................................................................................121 11.18 Constant class properties .............................................................................................................121 11.19 Abstract classes and virtual methods ...........................................................................................122 11.20 Polymorphism: dynamic method lookup.....................................................................................123 11.21 Class scope resolution operator :: ................................................................................................123 11.22 Out of block declarations .............................................................................................................124 11.23 Parameterized classes ..................................................................................................................125 11.24 Typedef class ...............................................................................................................................126 11.25 Classes and structures ..................................................................................................................126 11.26 Memory management ..................................................................................................................127 Section 12 Random Constraints .................................................................................................................. 128 12.1 Introduction (informative) ...........................................................................................................128 12.2 Overview......................................................................................................................................128 12.3 Random variables ........................................................................................................................131 12.4 Constraint blocks .........................................................................................................................132 12.5 Randomization methods ..............................................................................................................145 12.6 In-line constraints — randomize() with.......................................................................................147 12.7 Disabling random variables with rand_mode() ...........................................................................148 12.8 Controlling constraints with constraint_mode() ..........................................................................149 12.9 Dynamic constraint modification.................................................................................................150 12.10 In-line random variable control ...................................................................................................150 12.11 Randomization of scope variables — std::randomize()...............................................................151 12.12 Random number system functions and methods .........................................................................153 12.13Random stability ..........................................................................................................................154 12.14 Manually seeding randomize .......................................................................................................156 12.15 Random weighted case — randcase ............................................................................................157 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 x Copyright 2004 Accellera. All rights reserved . 12.16 Random sequence generation — randsequence...........................................................................158 Section 13 Interprocess Synchronization and Communication................................................................ 166 13.1 Introduction (informative) ...........................................................................................................166 13.2 Semaphores ..................................................................................................................................166 13.3 Mailboxes.....................................................................................................................................167 13.4 Parameterized mailboxes .............................................................................................................170 13.5 Event ............................................................................................................................................171 13.6 Event sequencing: wait_order() ...................................................................................................172 13.7 Event variables.............................................................................................................................173 Section 14 Scheduling Semantics................................................................................................................. 176 14.1 Execution of a hardware model and its verification environment ...............................................176 14.2 Event simulation ..........................................................................................................................176 14.3 The stratified event scheduler ......................................................................................................176 14.4 The PLI callback control points...................................................................................................180 Section 15 Clocking Blocks .......................................................................................................................... 181 15.1 Introduction (informative) ...........................................................................................................181 15.2 Clocking block declaration ..........................................................................................................181 15.3 Input and output skews ................................................................................................................183 15.4 Hierarchical expressions ..............................................................................................................184 15.5 Signals in multiple clocking blocks .............................................................................................185 15.6 Clocking block scope and lifetime...............................................................................................185 15.7 Multiple clocking blocks example ...............................................................................................185 15.8 Interfaces and clocking blocks.....................................................................................................186 15.9 Clocking block events..................................................................................................................187 15.10 Cycle delay: ## ............................................................................................................................187 15.11 Default clocking...........................................................................................................................188 15.12 Input sampling .............................................................................................................................189 15.13 Synchronous events .....................................................................................................................189 15.14 Synchronous drives......................................................................................................................190 Section 16 Program Block............................................................................................................................ 193 16.1 Introduction (informative) ...........................................................................................................193 16.2 The program construct .................................................................................................................193 16.3 Multiple programs........................................................................................................................195 16.4 Eliminating testbench races .........................................................................................................195 16.5 Blocking tasks in cycle/event mode.............................................................................................196 16.6 Program control tasks ..................................................................................................................196 Section 17 Assertions ................................................................................................................................... 198 17.1 Introduction (informative) ...........................................................................................................198 17.2 Immediate assertions....................................................................................................................198 17.3 Concurrent assertions overview...................................................................................................200 17.4 Boolean expressions ....................................................................................................................201 17.5 Sequences.....................................................................................................................................203 17.6 Declaring sequences ....................................................................................................................206 17.7 Sequence operations ....................................................................................................................208 17.8 Manipulating data in a sequence..................................................................................................224 17.9 Calling subroutines on match of a sequence................................................................................228 17.10 System functions..........................................................................................................................229 17.11 Declaring properties.....................................................................................................................229 17.12 Multiple clock support .................................................................................................................240 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. xi 17.13 Concurrent assertions...................................................................................................................246 17.14 Clock resolution ...........................................................................................................................252 17.15 Binding properties to scopes or instances....................................................................................258 17.16 The expect statement ...................................................................................................................259 Section 18 Hierarchy..................................................................................................................................... 261 18.1 Introduction (informative) ...........................................................................................................261 18.2 Packages.......................................................................................................................................261 18.3 Compilation unit support .............................................................................................................265 18.4 Top-level instance........................................................................................................................266 18.5 Module declarations.....................................................................................................................267 18.6 Nested modules............................................................................................................................267 18.7 Extern modules ............................................................................................................................269 18.8 Port declarations ..........................................................................................................................270 18.9 List of port expressions................................................................................................................271 18.10 Time unit and precision ...............................................................................................................271 18.11 Module instances .........................................................................................................................272 18.12 Port connection rules ...................................................................................................................276 18.13 Name spaces ................................................................................................................................277 18.14 Hierarchical names ......................................................................................................................278 Section 19 Interfaces ..................................................................................................................................... 279 19.1 Introduction (informative) ...........................................................................................................279 19.2 Interface syntax............................................................................................................................280 19.3 Ports in interfaces.........................................................................................................................284 19.4 Modports ......................................................................................................................................285 19.5 Interfaces and specify blocks .......................................................................................................291 19.6 Tasks and functions in interfaces.................................................................................................291 19.7 Parameterized interfaces ..............................................................................................................297 19.8 Virtual interfaces..........................................................................................................................299 19.9 Access to interface objects...........................................................................................................303 Section 20 Coverage...................................................................................................................................... 305 20.1 Introduction (informative) ...........................................................................................................305 20.2 Defining the coverage model: covergroup...................................................................................306 20.3 Using covergroup in classes ........................................................................................................308 20.4 Defining coverage points .............................................................................................................309 20.5 Defining cross coverage...............................................................................................................315 20.6 Specifying coverage options ........................................................................................................319 20.7 Predefined coverage methods ......................................................................................................324 20.8 Predefined coverage system tasks and functions .........................................................................324 20.9 Organization of option and type_option members ......................................................................324 Section 21 Parameters .................................................................................................................................. 326 21.1 Introduction (informative) ...........................................................................................................326 21.2 Parameter declaration syntax .......................................................................................................327 Section 22 Configuration Libraries............................................................................................................. 330 22.1 Introduction (informative) ...........................................................................................................330 22.2 Libraries .......................................................................................................................................330 Section 23 System Tasks and System Functions ........................................................................................ 331 23.1 Introduction (informative) ...........................................................................................................331 23.2 Elaboration-time typeof function.................................................................................................331 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 xii Copyright 2004 Accellera. All rights reserved . 23.3 Typename function ......................................................................................................................331 23.4 Expression size system function ..................................................................................................332 23.5 Range system function.................................................................................................................333 23.6 Shortreal conversions...................................................................................................................333 23.7 Array querying system functions .................................................................................................334 23.8 Assertion severity system tasks ...................................................................................................335 23.9 Assertion control system tasks.....................................................................................................336 23.10 Assertion system functions ..........................................................................................................336 23.11 Random number system functions...............................................................................................337 23.12 Program control ...........................................................................................................................337 23.13 Coverage system functions ..........................................................................................................337 23.14 Enhancements to Verilog-2001 system tasks ..............................................................................337 23.15 $readmemb and $readmemh........................................................................................................338 23.16 $writememb and $writememh .....................................................................................................338 23.17 File format considerations for multi-dimensional unpacked arrays ............................................339 23.18 System task arguments for multi-dimensional unpacked arrays .................................................340 Section 24 VCD Data .................................................................................................................................... 342 Section 25 Compiler Directives.................................................................................................................... 343 25.1 Introduction (informative) ...........................................................................................................343 25.2 ‘define macros..............................................................................................................................343 25.3 `include ........................................................................................................................................344 Section 26 Features under consideration for removal from SystemVerilog ........................................... 345 26.1 Introduction (informative) ...........................................................................................................345 26.2 Defparam statements....................................................................................................................345 26.3 Procedural assign and deassign statements..................................................................................345 Section 27 Direct Programming Interface (DPI) ....................................................................................... 347 27.1 Overview......................................................................................................................................347 27.2 Two layers of the DPI ..................................................................................................................348 27.3 Global name space of imported and exported functions..............................................................349 27.4 Imported tasks and functions .......................................................................................................349 27.5 Calling imported functions ..........................................................................................................355 27.6 Exported functions .......................................................................................................................356 27.7 Exported tasks..............................................................................................................................357 27.8 Disabling DPI tasks and functions...............................................................................................357 Section 28 SystemVerilog Assertion API .................................................................................................... 359 28.1 Requirements ...............................................................................................................................359 28.2 Extensions to VPI enumerations..................................................................................................359 28.3 Static information ........................................................................................................................360 28.4 Dynamic information ...................................................................................................................363 28.5 Control functions .........................................................................................................................366 Section 29 SystemVerilog Coverage API .................................................................................................... 368 29.1 Requirements ...............................................................................................................................368 29.2 SystemVerilog real-time coverage access ...................................................................................369 29.3 FSM recognition ..........................................................................................................................374 29.4 VPI coverage extensions..............................................................................................................377 Section 30 SystemVerilog Data Read API .................................................................................................. 381 30.1 Introduction (informative) ...........................................................................................................381 Accellera Extensions to Verilog-2001 SystemVerilog 3.1a Copyright 2004 Accellera. All rights reserved. xiii 30.2 Requirements ...............................................................................................................................381 30.3 Extensions to VPI enumerations..................................................................................................382 30.4 VPI object type additions.............................................................................................................383 30.5 Object model diagrams ................................................................................................................385 30.6 Usage extensions to VPI routines ................................................................................................387 30.7 VPI routines added in SystemVerilog .........................................................................................388 30.8 Reading data ................................................................................................................................389 30.9 Optionally unloading the data......................................................................................................399 30.10 Reading data from multiple databases and/or different read library providers ...........................399 30.11VPI routines extended in SystemVerilog.....................................................................................402 30.12VPI routines added in SystemVerilog .........................................................................................403 Section 31 SystemVerilog VPI Object Model............................................................................................. 407 31.1 Introduction (informative) ...........................................................................................................407 31.2 Instance .......................................................................................................................................409 31.3 Interface ......................................................................................................................................410 31.4 Program........................................................................................................................................410 31.5 Module (supersedes IEEE 1364-2001 26.6.1) ............................................................................411 31.6 Modport ......................................................................................................................................412 31.7 Interface tf decl ............................................................................................................................412 31.8 Ports (supersedes IEEE 1364-2001 26.6.5) .................................................................................413 31.9 Ref Obj.........................................................................................................................................414 31.10 Variables (supersedes IEEE 1364-2001 section 26.6.8) .............................................................416 31.11 Var Select (supersedes IEEE 1364-2001 26.6.8).........................................................................418 31.12 Typespec ......................................................................................................................................419 31.13 Variable Drivers and Loads (supersedes IEEE 1364-2001 26.6.23) ...........................................421 31.14 Instance Arrays (supersedes IEEE 1364-2001 26.6.2) ................................................................421 31.15 Scope (supersedes IEEE 1364-2001 26.6.3) ...............................................................................422 31.16 IO Declaration (supersedes IEEE 1364-2001 26.6.4) .................................................................423 31.17 Clocking Block ...........................................................................................................................424 31.18 Class Object Definition................................................................................................................425 31.19 Constraint, constraint ordering, distribution, ...............................................................................426 31.20 Constraint expression...................................................................................................................427 31.21 Class Variables ...........................................................................................................................428 31.23 Named Events (supersedes IEEE 1364-2001 26.6.11) ................................................................430 31.24 Task, Function Declaration (supersedes IEEE 1364-2001 26.6.18)............................................431 31.25 Alias Statement ...........................................................................................................................432 31.26 Frames (supersedes IEEE 1364-2001 26.6.20)............................................................................433 31.27 Threads.........................................................................................................................................434 31.28 tf call (supersedes IEEE 1364-2001 26.6.19) ..............................................................................435 31.29 Module path, path term (supersedes IEEE 1364-2001 26.6.15) .................................................436 31.30 Concurrent assertions ..................................................................................................................437 31.31 Property Decl ..............................................................................................................................437 31.32 Property Specification .................................................................................................................438 31.33 Multiclock Sequence Expression ................................................................................................439 31.34 Sequence Declaration .................................................................................................................440 31.35 Sequence Expression ..................................................................................................................441 31.36 Attribute (supersedes IEEE 1364-2001 26.6.42) ........................................................................442 31.37 Atomic Statement (supersedes IEEE 1364-2001 26.6.27) .........................................................443 31.38 If, if else, return, case, do while (supersedes IEEE 1364-2001 26.6.35, 26.6.36).......................444 31.39 waits, disables, expect, foreach (supersedes IEEE 1364 26.6.38) ...............................................445 31.40 Simple expressions (supersedes IEEE 1364-2001 26.6.25) ........................................................446 31.41 Expressions (supersedes IEEE 1364-2001 26.6.26) ....................................................................447 31.42 Event control (supersedes IEEE 1364-2001 26.6.30)..................................................................448 Accellera SystemVerilog 3.1a Extensions to Verilog-2001 xiv Copyright 2004 Accellera. All rights reserved . 31.43 Event stmt (supersedes IEEE 1364-2001 26.6.27) .....................................................................448 31.44 Process (supersedes IEEE 1364-2001 26.6.27) ..........................................................................449 31.45 Assignment (supersedes IEEE 1364-2001 26.6.28) ...................................................................449 Annex A Formal Syntax.............................................................................................................................. 451 Annex B Keywords ...................................................................................................................................... 488 Annex C Std Package ................................................................................................................................. 490 Annex D Linked Lists................................................................................................................................. 492 Annex E DPI C-layer .................................................................................................................................. 498 Annex F Include files .................................................................................................................................. 523 Annex G Inclusion of Foreign Language Code ......................................................................................... 529 Annex H Formal Semantics of Concurrent Assertions ............................................................................ 533 Annex I sv_vpi_user.h................................................................................................................................ 544 Annex J Glossary ........................................................................................................................................ 553 Annex K Bibliography................................................................................................................................. 555 Index 557
Table of Contents Preface 1. Introduction to Hibernate 1.1. Preface 1.2. Part 1 - The first Hibernate Application 1.2.1. The first class 1.2.2. The mapping file 1.2.3. Hibernate configuration 1.2.4. Building with Ant 1.2.5. Startup and helpers 1.2.6. Loading and storing objects 1.3. Part 2 - Mapping associations 1.3.1. Mapping the Person class 1.3.2. A unidirectional Set-based association 1.3.3. Working the association 1.3.4. Collection of values 1.3.5. Bi-directional associations 1.3.6. Working bi-directional links 1.4. Part 3 - The EventManager web application 1.4.1. Writing the basic servlet 1.4.2. Processing and rendering 1.4.3. Deploying and testing 1.5. Summary 2. Architecture 2.1. Overview 2.2. Instance states 2.3. JMX Integration 2.4. JCA Support 2.5. Contextual Sessions 3. Configuration 3.1. Programmatic configuration 3.2. Obtaining a SessionFactory 3.3. JDBC connections 3.4. Optional configuration properties 3.4.1. SQL Dialects 3.4.2. Outer Join Fetching 3.4.3. Binary Streams 3.4.4. Second-level and query cache 3.4.5. Query Language Substitution 3.4.6. Hibernate statistics 3.5. Logging 3.6. Implementing a NamingStrategy 3.7. XML configuration file 3.8. J2EE Application Server integration 3.8.1. Transaction strategy configuration 3.8.2. JNDI-bound SessionFactory 3.8.3. Current Session context management with JTA 3.8.4. JMX deployment 4. Persistent Classes 4.1. A simple POJO example 4.1.1. Implement a no-argument constructor 4.1.2. Provide an identifier property (optional) 4.1.3. Prefer non-final classes (optional) 4.1.4. Declare accessors and mutators for persistent fields (optional) 4.2. Implementing inheritance 4.3. Implementing equals() and hashCode() 4.4. Dynamic models 4.5. Tuplizers 5. Basic O/R Mapping 5.1. Mapping declaration 5.1.1. Doctype 5.1.2. hibernate-mapping 5.1.3. class 5.1.4. id 5.1.4.1. Generator 5.1.4.2. Hi/lo algorithm 5.1.4.3. UUID algorithm 5.1.4.4. Identity columns and sequences 5.1.4.5. Assigned identifiers 5.1.4.6. Primary keys assigned by triggers 5.1.5. composite-id 5.1.6. discriminator 5.1.7. version (optional) 5.1.8. timestamp (optional) 5.1.9. property 5.1.10. many-to-one 5.1.11. one-to-one 5.1.12. natural-id 5.1.13. component, dynamic-component 5.1.14. properties 5.1.15. subclass 5.1.16. joined-subclass 5.1.17. union-subclass 5.1.18. join 5.1.19. key 5.1.20. column and formula elements 5.1.21. import 5.1.22. any 5.2. Hibernate Types 5.2.1. Entities and values 5.2.2. Basic value types 5.2.3. Custom value types 5.3. Mapping a class more than once 5.4. SQL quoted identifiers 5.5. Metadata alternatives 5.5.1. Using XDoclet markup 5.5.2. Using JDK 5.0 Annotations 5.6. Generated Properties 5.7. Auxiliary Database Objects 6. Collection Mapping 6.1. Persistent collections 6.2. Collection mappings 6.2.1. Collection foreign keys 6.2.2. Collection elements 6.2.3. Indexed collections 6.2.4. Collections of values and many-to-many associations 6.2.5. One-to-many associations 6.3. Advanced collection mappings 6.3.1. Sorted collections 6.3.2. Bidirectional associations 6.3.3. Bidirectional associations with indexed collections 6.3.4. Ternary associations 6.3.5. Using an <idbag> 6.4. Collection examples 7. Association Mappings 7.1. Introduction 7.2. Unidirectional associations 7.2.1. many to one 7.2.2. one to one 7.2.3. one to many 7.3. Unidirectional associations with join tables 7.3.1. one to many 7.3.2. many to one 7.3.3. one to one 7.3.4. many to many 7.4. Bidirectional associations 7.4.1. one to many / many to one 7.4.2. one to one 7.5. Bidirectional associations with join tables 7.5.1. one to many / many to one 7.5.2. one to one 7.5.3. many to many 7.6. More complex association mappings 8. Component Mapping 8.1. Dependent objects 8.2. Collections of dependent objects 8.3. Components as Map indices 8.4. Components as composite identifiers 8.5. Dynamic components 9. Inheritance Mapping 9.1. The Three Strategies 9.1.1. Table per class hierarchy 9.1.2. Table per subclass 9.1.3. Table per subclass, using a discriminator 9.1.4. Mixing table per class hierarchy with table per subclass 9.1.5. Table per concrete class 9.1.6. Table per concrete class, using implicit polymorphism 9.1.7. Mixing implicit polymorphism with other inheritance mappings 9.2. Limitations 10. Working with objects 10.1. Hibernate object states 10.2. Making objects persistent 10.3. Loading an object 10.4. Querying 10.4.1. Executing queries 10.4.1.1. Iterating results 10.4.1.2. Queries that return tuples 10.4.1.3. Scalar results 10.4.1.4. Bind parameters 10.4.1.5. Pagination 10.4.1.6. Scrollable iteration 10.4.1.7. Externalizing named queries 10.4.2. Filtering collections 10.4.3. Criteria queries 10.4.4. Queries in native SQL 10.5. Modifying persistent objects 10.6. Modifying detached objects 10.7. Automatic state detection 10.8. Deleting persistent objects 10.9. Replicating object between two different datastores 10.10. Flushing the Session 10.11. Transitive persistence 10.12. Using metadata 11. Transactions And Concurrency 11.1. Session and transaction scopes 11.1.1. Unit of work 11.1.2. Long conversations 11.1.3. Considering object identity 11.1.4. Common issues 11.2. Database transaction demarcation 11.2.1. Non-managed environment 11.2.2. Using JTA 11.2.3. Exception handling 11.2.4. Transaction timeout 11.3. Optimistic concurrency control 11.3.1. Application version checking 11.3.2. Extended session and automatic versioning 11.3.3. Detached objects and automatic versioning 11.3.4. Customizing automatic versioning 11.4. Pessimistic Locking 11.5. Connection Release Modes 12. Interceptors and events 12.1. Interceptors 12.2. Event system 12.3. Hibernate declarative security 13. Batch processing 13.1. Batch inserts 13.2. Batch updates 13.3. The StatelessSession interface 13.4. DML-style operations 14. HQL: The Hibernate Query Language 14.1. Case Sensitivity 14.2. The from clause 14.3. Associations and joins 14.4. Forms of join syntax 14.5. The select clause 14.6. Aggregate functions 14.7. Polymorphic queries 14.8. The where clause 14.9. Expressions 14.10. The order by clause 14.11. The group by clause 14.12. Subqueries 14.13. HQL examples 14.14. Bulk update and delete 14.15. Tips & Tricks 15. Criteria Queries 15.1. Creating a Criteria instance 15.2. Narrowing the result set 15.3. Ordering the results 15.4. Associations 15.5. Dynamic association fetching 15.6. Example queries 15.7. Projections, aggregation and grouping 15.8. Detached queries and subqueries 15.9. Queries by natural identifier 16. Native SQL 16.1. Using a SQLQuery 16.2. Alias and property references 16.3. Named SQL queries 16.3.1. Using return-property to explicitly specify column/alias names 16.3.2. Using stored procedures for querying 16.3.2.1. Rules/limitations for using stored procedures 16.4. Custom SQL for create, update and delete 16.5. Custom SQL for loading 17. Filtering data 17.1. Hibernate filters 18. XML Mapping 18.1. Working with XML data 18.1.1. Specifying XML and class mapping together 18.1.2. Specifying only an XML mapping 18.2. XML mapping metadata 18.3. Manipulating XML data 19. Improving performance 19.1. Fetching strategies 19.1.1. Working with lazy associations 19.1.2. Tuning fetch strategies 19.1.3. Single-ended association proxies 19.1.4. Initializing collections and proxies 19.1.5. Using batch fetching 19.1.6. Using subselect fetching 19.1.7. Using lazy property fetching 19.2. The Second Level Cache 19.2.1. Cache mappings 19.2.2. Strategy: read only 19.2.3. Strategy: read/write 19.2.4. Strategy: nonstrict read/write 19.2.5. Strategy: transactional 19.3. Managing the caches 19.4. The Query Cache 19.5. Understanding Collection performance 19.5.1. Taxonomy 19.5.2. Lists, maps, idbags and sets are the most efficient collections to update 19.5.3. Bags and lists are the most efficient inverse collections 19.5.4. One shot delete 19.6. Monitoring performance 19.6.1. Monitoring a SessionFactory 19.6.2. Metrics 20. Toolset Guide 20.1. Automatic schema generation 20.1.1. Customizing the schema 20.1.2. Running the tool 20.1.3. Properties 20.1.4. Using Ant 20.1.5. Incremental schema updates 20.1.6. Using Ant for incremental schema updates 20.1.7. Schema validation 20.1.8. Using Ant for schema validation 21. Example: Parent/Child 21.1. A note about collections 21.2. Bidirectional one-to-many 21.3. Cascading lifecycle 21.4. Cascades and unsaved-value 21.5. Conclusion 22. Example: Weblog Application 22.1. Persistent Classes 22.2. Hibernate Mappings 22.3. Hibernate Code 23. Example: Various Mappings 23.1. Employer/Employee 23.2. Author/Work 23.3. Customer/Order/Product 23.4. Miscellaneous example mappings 23.4.1. "Typed" one-to-one association 23.4.2. Composite key example 23.4.3. Many-to-many with shared composite key attribute 23.4.4. Content based discrimination 23.4.5. Associations on alternate keys 24. Best Practices

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