FPGA学习层次化设计例5

最新推荐文章于 2024-09-27 21:53:49 发布

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最新推荐文章于 2024-09-27 21:53:49 发布

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本文链接：https://blog.csdn.net/qq_51152795/article/details/130955780

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层次化设计(例5）

设计目标

输入：A[7:0],B[7:0],C[7:0],D[7:0],SEL[3:0]
功能：SEL=0,P=A+B+C+D;
SEL=1,P=A;
SEL=2,P=B;
SEL=3,P=C;
SEL=4,P=D;
SEL为其他值，P=0;

框图

请添加图片描述

代码

顶层代码TEST5_TOP

module TEST5_TOP (
    input wire [7:0]A,
    input wire [7:0]B,
    input wire [7:0]C,
    input wire [7:0]D,
    input wire [3:0]SEL,
    output wire [26:0]P
);

wire [8:0]add_result;

ADD ADD_1(
    .A(A),
    .B(B),
    .C(C),
    .D(D),
    .add_result(add_result)
);

MUX MUX_1(
    .M1(A),
    .M2(B),
    .M3(C),
    .M4(D),
    .M5(add_result),
    .SEL(SEL),
    .P(P)
);
    
endmodule

ADD模块

 module ADD (
    input wire [7:0]A,
    input wire [7:0]B,
    input wire [7:0]C,
    input wire [7:0]D,
    output wire [8:0] add_result
);
    
assign add_result = A + B + C + D;

endmodule

MUX模块

 module MUX (
    input wire [7:0]M1,
    input wire [7:0]M2,
    input wire [7:0]M3,
    input wire [7:0]M4,
    input wire [8:0]M5,
    input wire [3:0]SEL,
    output wire [8:0] P
);
    
assign P = (SEL == 4'd0)?M5:(
            (SEL == 4'd1)?M1:(
            (SEL == 4'd2)?M2:(
            (SEL == 4'd3)?M3:(
            (SEL == 4'd4)?M4:
            0))));


endmodule

tb文件

 `timescale 1ns/1ps

module TEST5_TOP_tb ();

reg [7:0]A;
reg [7:0]B;
reg [7:0]C;
reg [7:0]D;
reg [3:0]SEL;
wire [8:0]P;

initial begin
    A = 8'd1;
    B = 8'd1;
    C = 8'd1;
    D = 8'd1;
    SEL= 4'd1;
end

always #10 A = {$random} % 256;
always #10 B = {$random} % 256;
always #10 C = {$random} % 256;
always #10 D = {$random} % 256;
always #10 SEL = {$random} % 17;


TEST5_TOP TEST5_TOP_1(
    .A(A),
    .B(B),
    .C(C),
    .D(D),
    .SEL(SEL),
    .P(P)
);

endmodule