Verilog语法基础HDL Bits训练10

Circuits:Sequential Logic:Latches and Flip-Flops

一、D flip-flop

一个简单的D触发器，输出q在每个时钟上升沿根据d变化

• RTL代码

module top_module (
    input clk,    // Clocks are used in sequential circuits
    input d,
    output reg q );//

    always @(posedge clk)
        q <= d;

endmodule

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二、D flip-flops

创建8个DFF触发器

• RTL代码

module top_module (
    input clk,
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk)
        q <= d;

endmodule

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三、DFF with reset

在D触发器的基础上加一个同步复位控制，根据时钟的变化而起作用

• RTL代码

module top_module (
    input clk,
    input reset,            // Synchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk)
        if(reset)
            q <= 1'b0;
   		else
            q <= d;

endmodule

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四、DFF with reset value

在D触发器中加入同步复位，要求复位时数值为十六进制的34

• RTL代码

module top_module (
    input clk,
    input reset,
    input [7:0] d,
    output [7:0] q
);
    always @(negedge clk)
        if(reset)
            q <= 8'h34;
   		else
            q <= d;

endmodule

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五、DFF with asynchronous reset

在D触发器中加入异步复位

• RTL代码

module top_module (
    input clk,
    input areset,   // active high asynchronous reset
    input [7:0] d,
    output [7:0] q
);
    always @(posedge clk or posedge areset)
        if(areset)
            q <= 1'b0;
   		else
            q <= d;

endmodule

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六、DFF with byte enable

• RTL代码

module top_module (
    input clk,
    input resetn,
    input [1:0] byteena,
    input [15:0] d,
    output [15:0] q
);
    always @(posedge clk)
        if(!resetn)
            q <= 1'b0;
    	else
            begin
                q[15:8] <= (byteena[1])? d[15:8] : q[15:8] ;
                q[7:0] <= (byteena[0])? d[7:0] : q[7:0];
            end
    
endmodule

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七、D Latch

是一个锁存器，一般在Verilog中不是故意设计出来的锁存器是错误的，要注意避免锁存器的出现，因为锁存器不仅仅会使设计出现意料之外的错误，也会大幅占用资源

• RTL代码

module top_module (
    input d, 
    input ena,
    output q);
    
    assign q = (ena)? d : q;

endmodule

八、DFF

一个异步复位的D触发器

• RTL代码

module top_module (
    input clk,
    input d, 
    input ar,   // asynchronous reset
    output q);
    
    always @(posedge clk or posedge ar)
        if(ar)
            q <= 1'b0;
    	else
			q <= d;

endmodule

九、DFF

一个同步复位的D触发器

• RTL代码

module top_module (
    input clk,
    input d, 
    input r,   // synchronous reset
    output q);
    
    always @(posedge clk)
        if(r)
            q <= 1'b0;
    	else
            q <= d;

endmodule

十、DFF + gate

一个门电路加一个D触发器

• RTL代码

module top_module (
    input clk,
    input in, 
    output out);
    
    always @(posedge clk)
        out <= out ^ in;

endmodule

十一、Mux and DFF

• RTL代码

module top_module (
	input clk,
	input L,
	input r_in,
	input q_in,
	output reg Q);
    
    always @(posedge clk)
        Q <= (L)? r_in:q_in;

endmodule

十二、Mux and DFF

• RTL代码

module top_module (
    input clk,
    input w, R, E, L,
    output Q
);
    
    always @(posedge clk)
        Q <= (L)? R:((E)? w:Q);

endmodule

十三、DFFs and gates

• RTL代码

module top_module (
    input clk,
    input x,
    output z
); 
    wire q0,q1,q2;
    always @(posedge clk)
        begin
           q0 <= q0 ^ x;
           q1 <-=~q1 & x;
           q2 <= ~q2 | x;
        end
    
    assign z = ~(q0 | q1 | q2);

endmodule

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十四、Create circuit form truth table

设计一个JK触发器

• RTL代码

module top_module (
    input clk,
    input j,
    input k,
    output Q); 
    
    always @(posedge clk)
        if(!j & !k)
            Q <= Q;
    	else if(!j & k)
        	Q <= 1'b0;
    	else if(j & ~k)
        	Q <=1'b1;
    	else
            Q <= ~Q;

endmodule

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十五、Detect an edge

边沿检测，具体操作就是打一拍，然后做与运算

• RTL代码

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0]in_t;
    always @(posedge clk)
        begin
           in_t <= in;
           pedge <= ~in_t & in;
        end

endmodule

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十六、Detect both edge

• RTL代码

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] anyedge
);
    reg [7:0]in_t;
    always @(posedge clk)
        begin
        	in_t <= in;
    		anyedge <= in_t ^ in;
        end

endmodule

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十七、Edge captrue register

• RTL代码

module top_module (
    input clk,
    input reset,
    input [31:0] in,
    output [31:0] out
);
    reg [31:0]in_t;
    always @(posedge clk)
        begin
           	in_t <= in;
            if(reset)
          		out <= 1'b0;
            else
				out <= in_t & ~in | out;
        end
    
endmodule

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十八、Dual-edge triggered flip-flop

• RTL代码

module top_module (
    input clk,
    input d,
    output q
);
    reg q1,q2;
    always @(posedge clk)
        q1 <= d;
    
    always @(negedge clk)
        q2 <= d;
    
    assign q = (clk)? q1:q2;
            
endmodule

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