数电——闹钟

闹钟

module clock(key_0,key_1,key_2,Q1,Q2,Q3,Q4,min,s,clock,buzzer  );
    input  key_0;//分键
    input  key_1;//秒键
    input  key_2;//启动，暂停键,key_2=0暂停，key_2=1启动
    output reg [5:0]min=6'd0;
    output reg[5:0] s=6'd0;   
    output  reg [6:0] Q1;
    output reg [6:0] Q2;
    output reg[6:0] Q3;
    output reg [6:0]Q4;
    input clock;
   reg [3:0]min_shi;
   reg [3:0]min_ge;
   reg [3:0]s_shi;
   reg [3:0]s_ge;
    reg zheng;                                                                                                                                                                                                                                                                                                                                                                                                   
    reg count=0;//count=1开始计时，count=0停止计时
    reg set=0;//设置状态，如果为1，则为设置状态
    output reg buzzer=0;//蜂鸣器，当为1的时候蜂鸣，为0的时候停止
    always@(posedge key_0 or posedge key_1)//分键或者秒键变化之后执行
    begin
        if((key_0&key_1)==1)//如果同时按下分键与秒键
         begin
            count=0;//停止计数
             set=1;//转到设置状态
            min=6'd0;s=6'd0;//重置
         end
        if((set&!(key_1&key_0)==1))//此时到设置状态
         begin
             if(key_0==1)//如果分键按下
                begin
                    if(min==6'd99)
                        min=6'd0;
                    else
                         min=min+6'd1;
                 end
             else if(key_1==1)//如果秒键按下
                begin
                    if(s==6'd59)
                     s=6'd0;
                     else
                     s=s+6'd1;
                 end
           end
  end
 always@(set)
   begin
    if(min==6'd0&&s==6'd0)
      zheng=1;
    else
      zheng=0;
    end

always@(posedge clock)//按下启动暂停键之后,使其随时间计数
    if(count==1)//如果启动键为1，则开始计时
     begin
       if(zheng==1)//正计时
         begin
           if(s<6'd59)
           s=s+1;
           else if(s==6'd59)
           begin
            s=6'd0;
            min=min+1;
          end
         end
   else//倒计时
 begin
   begin
      if(s>6'd0)
       s=s-6'd1;
      else if(s==6'd0&&min!=6'd0)
       begin
       s=6'd59;
       min=min-6'd1;
       end
       else
       begin
       buzzer=1;//当分秒都为1时，蜂鸣器响
       end
    end
    end
    end
always@( posedge key_2)//如果按下启动暂停键
   begin
    if(buzzer==1)
     begin
      buzzer<=0;
       set<=1;
       count<=0;
     end
   else
    begin
     count<=~count;//每按一次计时取反
     set<=0;//此时如果在设置状态，跳出设置状态
    end
   end
always@(min)
  begin
  min_shi<=min/10;
  min_ge<=min%10;
  end
always@(s)
  begin
  s_shi<=s/10;
  s_ge<=s%10;
  end
always @ (min_shi)
  case(min_shi)
   4'b0000: Q1<=7'b0111111;
   4'b0001: Q1<=7'b0000110;
   4'b0010: Q1<=7'b1011011;
   4'b0011: Q1<=7'b1001111;
   4'b0100: Q1<=7'b1100110;
   4'b0101: Q1<=7'b1101101;
   4'b0110: Q1<=7'b1111101;
   4'b0111: Q1<=7'b0000111;
   4'b1000: Q1<=7'b1111111;
   4'b1001: Q1<=7'b1101111;
  default: Q1<=7'b0000000;
  endcase
  always @ (min_ge)
  case(min_ge)
   4'b0000: Q2<=7'b0111111;
   4'b0001: Q2<=7'b0000110;
   4'b0010: Q2<=7'b1011011;
   4'b0011: Q2<=7'b1001111;
   4'b0100: Q2<=7'b1100110;
   4'b0101: Q2<=7'b1101101;
   4'b0110: Q2<=7'b1111101;
   4'b0111: Q2<=7'b0000111;
   4'b1000: Q2<=7'b1111111;
   4'b1001: Q2<=7'b1101111;
  default: Q2<=7'b0000000;
  endcase
  always @ (s_shi)
  case(s_shi)
   4'b0000: Q3<=7'b0111111;
   4'b0001: Q3<=7'b0000110;
   4'b0010: Q3<=7'b1011011;
   4'b0011: Q3<=7'b1001111;
   4'b0100: Q3<=7'b1100110;
   4'b0101: Q3<=7'b1101101;
   4'b0110: Q3<=7'b1111101;
   4'b0111: Q3<=7'b0000111;
   4'b1000: Q3<=7'b1111111;
   4'b1001: Q3<=7'b1101111;
  default: Q3<=7'b0000000;
  endcase
  always @ (s_ge)
  case(s_ge)
   4'b0000: Q4<=7'b0111111;
   4'b0001: Q4<=7'b0000110;
   4'b0010: Q4<=7'b1011011;
   4'b0011: Q4<=7'b1001111;
   4'b0100: Q4<=7'b1100110;
   4'b0101: Q4<=7'b1101101;
   4'b0110: Q4<=7'b1111101;
   4'b0111: Q4<=7'b0000111;
   4'b1000: Q4<=7'b1111111;
   4'b1001: Q4<=7'b1101111;
  default: Q4<=7'b0000000;
  endcase

endmodule

2.testbench文件记录

module test_clock( );
wire [6:0] Q1;
wire [6:0] Q2;
wire [6:0] Q3;
wire [6:0] Q4;
reg key_0;
reg key_1;
reg key_2;
wire [5:0]min;
wire [5:0]s;
reg clock;
wire buzzer;

clock unit(.buzzer(buzzer),.clock(clock),.Q1(Q1),.Q2(Q2),.Q3(Q3),.Q4(Q4),.key_0(key_0),.key_1(key_1),.key_2(key_2),.min(min),.s(s));
initial
begin
clock=0;//倒计数
key_2=0;
key_0=0;key_1=0;
#10 key_0=1;key_1=1;
#10 key_0=~key_0;key_1=0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_0=~key_0;
#10 key_1=~key_1;
#10 key_1=~key_1;
#10 key_1=~key_1;
#10 key_1=~key_1;
#10 key_1=~key_1;
#10 key_1=~key_1;
#10 key_2=1;
#10 key_2=0;
#10 key_2=1;
#10 key_2=0;
#10 key_2=1;
#10 key_2=0;
#7000 key_2=1;
#10 key_2=0;

end
always #10 clock=~clock;
endmodule