新思科技招聘 | 十一月热招职位（外企内推哦）

最新推荐文章于 2025-05-23 14:35:40 发布

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shevary

最新推荐文章于 2025-05-23 14:35:40 发布

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分类专栏：招聘找工作 IC 文章标签：科技单片机硬件工程驱动开发求职招聘

本文链接：https://blog.csdn.net/shevary/article/details/128050870

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新思科技正在招聘多个关键职位，包括IP Subsystem Design Engineer、Analog Design Engineer、ASIC Digital Design/Verification Engineer等。工作地点分布在北京、上海、深圳、武汉等地。公司提供优厚待遇，包括外企福利、超长年假及人性化工作安排。有意者可将简历发送至指定邮箱或通过私人联系方式进行内推。

摘要生成于 C知道，由 DeepSeek-R1 满血版支持，前往体验 >

open岗位：
1、IP Subsystem Design Engineer (PCIE/USB) 北京/上海/深圳
2、Analog Design Engineer, Staff武汉
3、ASIC Digital Design/Verification Engineer武汉/上海
4、Bus Development Mgr上海
5、Product Solution Sales Manager (Verification Platform) 上海
6、Interface IP Application EnSOC Engineer上海/北京/深圳/武汉/西安
7、SOC Engineer上海/北京/深圳/武汉
感兴趣的铁子欢迎砸简历哈：lisa_sm@foxmail.com
或者私v: shevary (备注：内推+岗位+地点)

福利：近几年IC行业的待遇很nice哦，外企福利自不必说，超长年假（18天起）+ 人性化管理（弹性上班时间、支持在家办公等）+ 下午茶等等等
还有超nice的同事哦，快砸简历吧

----岗位详细说明---

1、IP Subsystem Design Engineer (PCIE/USB) 北京/上海/深圳
Job Description：

We’re looking for an IP Subsystem Design and Application Engineer to join the team. Does this sound like a good role for you? This role involves developing and verifying integrated Interface IP Subsystems. Additionally, you’d:
Create design and verification specifications
Determine architecture design, logic design, test bench design, and test cases
Define module interfaces and formats
Evaluate and exercise various aspects of the development flow which may include such items as RTL development, functional simulation, constraint development, design for test logic, synthesis, timing analysis, power analysis, and verification coverage metrics

Key qualifications:

Bachelor’s and/or master’s degree in electrical and/or Electronic Engineering, Computer Engineering or Computer Science
Minimum 5 years of IP and/or ASIC Design/Verification/Applications experience required
Hands-on experience in RTL coding, verification, synthesis, static timing analysis, equivalence check, etc.
Domain knowledge of interface standards: PCIe, USB, Ethernet or DDR
Good communication skills while interacting with internal teams and customers

Preferred Experience:

Experience in Design Compiler, Fusion Compiler, Spyglass or VC
Experience in UVM methodology
Experience in DesignWare Cores
Experience in TCL, Perl, Python, or other shell scripting

2、Analog Design Engineer, Staff 武汉
Responsibilities：

involve in analog design and mixed signal IP design, especially the design of high-speed SerDes
Work with a cross functional design team of analog and digital designers from a wide variety of backgrounds
Design innovative analog and mixed-signal integr

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