Verilog刷题笔记52

题目：
Fsm serial
In many (older) serial communications protocols, each data byte is sent along with a start bit and a stop bit, to help the receiver delimit bytes from the stream of bits. One common scheme is to use one start bit (0), 8 data bits, and 1 stop bit (1). The line is also at logic 1 when nothing is being transmitted (idle).

解题：

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 

    parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,s9=9,s10=10,s11=11;
    reg [3:0]state,next_state;
    always@(posedge clk)begin
        if(reset)
            state=s0;
        else
            state=next_state;
    end
    always@(*)begin
        case(state)
            s0:next_state=(in==0)?s11:s0;
            s11:next_state=s1;
            s1:next_state=s2;
            s2:next_state=s3;
            s3:next_state=s4;
            s4:next_state=s5;
            s5:next_state=s6;
            s6:next_state=s7;
            s7:next_state=s8;
            s8:next_state=(in==1)?s9:s10;
            s9:next_state=(in==0)?s11:s0;
            s10:next_state=(in==1)?s0:s10;
            default:next_state=s0;
        endcase
    end
    assign done=(state==s9)?1:0;
endmodule

结果正确

网络上看到的好的解题方法:
简单粗暴方法:
空闲状态IDLE，在接收到输入in=0，意味着传输的开始跳到START，接着跳到BIT1-8状态接，在BIT8再次判断in，如果接收到1，则此次传输结束跳到STOP，如果不是，意味这次传输数据无效，等接收到in=1，此次传输结束。
状态转移图：

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 
    parameter [3:0] IDLE  = 4'd0;
    parameter [3:0] START = 4'd1;
    parameter [3:0] BIT1  = 4'd2;
    parameter [3:0] BIT2  = 4'd3;
    parameter [3:0] BIT3  = 4'd4;
    parameter [3:0] BIT4  = 4'd5;
    parameter [3:0] BIT5  = 4'd6;
    parameter [3:0] BIT6  = 4'd7;
    parameter [3:0] BIT7  = 4'd8;
    parameter [3:0] BIT8  = 4'd9;
    parameter [3:0] STOP  = 4'd10;
    parameter [3:0] ERROR  = 4'd11;
    reg [3:0] state,nstate;
    
    always @(posedge clk)begin
        if(reset)begin
            state <= IDLE;
        end
        else begin
           state <= nstate; 
        end
    end
    
    always @(*)begin
       nstate = IDLE;
        case(state)
            IDLE: nstate = in? IDLE:START;
            START:nstate = BIT1;
            BIT1: nstate = BIT2;
            BIT2: nstate = BIT3;
            BIT3: nstate = BIT4;
            BIT4: nstate = BIT5;
            BIT5: nstate = BIT6;
            BIT6: nstate = BIT7;
            BIT7: nstate = BIT8;
            BIT8: nstate = in? STOP:ERROR;
            STOP: nstate = in? IDLE:START;
            ERROR: nstate = in? IDLE:ERROR;
            default: nstate = IDLE;
        endcase
    end
    
    assign done = (state == STOP);
endmodule

还有一种缩减状态机数量方法：对于中间过程很多的情况，我们无法全部写出，这时候可以使用循环整型变量来计数当前的时钟周期，从而描述复杂状态的转移。以下代码采用变量cnt记录过去的个时钟周期数，而不是使用八个状态描述接收过程。

module top_module(
    input clk,
    input in,
    input reset,    // Synchronous reset
    output done
); 

    localparam idle = 0;
    localparam start = 1;
    localparam data = 2;
    localparam stop =3;
    localparam error = 4;
    
    reg[2:0] state, next_state;
    reg[3:0] cnt;
    reg done_r;
    
//transition
    always@(*)begin
        case(state)
            idle:next_state=in?idle:start;
            start:next_state=data;
            data:next_state=(cnt==8)?(in?stop:error):data;
            stop:next_state=in?idle:start;
            error:next_state=in?idle:error;
        endcase
    end
    
//state
    always@(posedge clk)begin
        if(reset)
            state <= idle;
        else
            state <= next_state;
    end
    
//cnt
    always@(posedge clk)begin
        if(reset)
            cnt<=0;
        else
            case(next_state)
                start:cnt<=0;
                data:cnt<=cnt+1;
                default:cnt<=cnt;
            endcase
    end
    
//done_r
    always@(posedge clk)
        case(next_state)
            stop:done_r <= 1;
            default:done_r <= 0;
        endcase
    
    assign done = done_r;
    
endmodule