modelsim仿真方法
创建工程-compile-
错误1:
Error: D:/altera/modelsim_ase/examples/led.vhd(2): near "EOF": syntax error
解决:选择语言错误 应选择verilog而不是VHDL
和modelsim关联:
quartus ii:Tool-Options-General-EDA Tool Options-Modelsim-Altera
自动生成Test Bench:
Processing-Start-Start Test Bench Template Writer
关联仿真:
Assignments-Settings-Simulation-选择语言和文件进行仿真
开始仿真:
Tools-Run EDA Simulation tool-EDA RTL Simulation