Means Timing paths between these clock domains are false, but only one clock can exist in the design at the same time. ETS/Tempus will filter out the SI interactions of nets/paths between these groups.
To phrase it differently, if the clocks are exclusive, then there should be no SI victim/aggressor interaction at all between nets clocked by physically excluded clocks.
asynchronous
If two clocks are asynchronous, it means that they don't have any phase relationship among them at all. So instead of using definite timing windows based on arrival times/skew etc, the tool will use infinite timing windows when calculating aggressors and victims, therefore you will see maximum SI impact.
logically_exclusive
Logically exclusive means the timing paths between these clock domains are false, but both clocks can exist in the design at the same time, so SI interactions between paths in these domains should still be considered. However crosstalk analysis will be done with regular timing windows based on arrival times/skew etc.
Assume that from your chip two data buses are going to UART module or USART. One of them will transmit, other will recieve. One is triggered by Tclk other by Rclk (same frequency say) Now, they can co-exist but if our design is not duplex (i.e only one of them can exist at a time) then we have to make sure that STA tool does not check for any violation between these two clocks. thats when we set logically_exclusive. Now, say it is duplex... the two clocks can co-exist and work on different paths.. so they might not be having any timing paths in common but during SI analysis it has to be taken into consideration since both of them could be switching at same time (same 0r opposite direction) and thus make an SI impact. So, it cannot be set as physically exclusive.
Physically exclusive would be something like two clocks going into a mux and coming out. According to SEL only one of them can exist and thus SI computation on both would be overtly pessimistic.
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