testbench通用模板

module syn_fifo_tb(

    );
 //--------参数及端口定义，注意输入与时钟复位要定义为reg型---------
	parameter DATA_WIDTH = 8;
    parameter DATA_DEPTH = 8;
  
    reg i_clk;
    reg i_rst;
    
    //write port
    reg wr_en;
    reg [DATA_WIDTH - 1 : 0] wr_data;
    wire wr_full;
    //read port
    reg rd_en;
    wire [DATA_WIDTH - 1 : 0] rd_data;
    wire rd_empty;
    
//------------------------时钟激励，采用forever-----------///

    initial begin
    	i_clk = 0;
    	forever begin
    		#5 i_clk = ~i_clk;
    	end
    end

//数据初始化及后续输入，包括复位,采用@(negedge i_clk)或者@(posedge i_clk)的方式在时钟边沿添加输入//
    initial begin
    	
    	i_rst = 1;
    	wr_en = 0;
    	rd_en = 0;

    	@(negedge i_clk) i_rst = 0;
    	@(negedge i_clk) wr_en = 1;
    	wr_data = $random;

    	repeat(3) begin
    		@(negedge i_clk)
    		wr_data = $random;	
    	end
    	
    	

    	@(negedge i_clk)
    	wr_en = 0;
    	rd_en = 1;

    	repeat(3) begin
    		@(negedge i_clk);	
    	end

    	@(negedge i_clk)
    	rd_en = 0;
    	wr_en = 1;
    	wr_data = $random;

    	repeat(7) begin   		
    		@(negedge i_clk)
    		wr_data = $random;
    	end

    	#20 $finish;


    end

//实例化模块
	syn_fifo #(.DATA_WIDTH(DATA_WIDTH),.DATA_DEPTH(DATA_DEPTH))
	inst_syn_fifo
		(
			.i_clk    (i_clk),
			.i_rst    (i_rst),
			.wr_en    (wr_en),
			.wr_data  (wr_data),
			.wr_full  (wr_full),
			.rd_en    (rd_en),
			.rd_data  (rd_data),
			.rd_empty (rd_empty)
		);

endmodule

这里用了一个之前的fifo的激励文件作为模板。