IIC-BUS INTERFACE
2.1 OVERVIEW OF IIC-BUS INTERFACE
The S5PV210 RISC microprocessor supports four multi-master I2C bus serial interfaces. To carry information
between bus masters and peripheral devices connected to the I2C bus, a dedicated Serial Data Line (SDA) and
an Serial Clock Line (SCL) is used. Both SDA and SCL lines are bi-directional.
In multi-master I2C-bus mode, multiple S5PV210 RISC microprocessors receive or transmit serial data to or from
slave devices. The master S5PV210 initiates and terminates a data transfer over the I2C bus. The I2C bus in the
S5PV210 uses a standard bus arbitration procedure.
To control multi-master I2C-bus operations, values must be written to the following registers:
• Multi-master I2C-bus control register- I2CCON
• Multi-master I2C-bus control/status register- I2CSTAT
• Multi-master I2C-bus Tx/Rx data shift register- I2CDS
• Multi-master I2C-bus address register- I2CADD
2.1 OVERVIEW OF IIC-BUS INTERFACE
The S5PV210 RISC microprocessor supports four multi-master I2C bus serial interfaces. To carry information
between bus masters and peripheral devices connected to the I2C bus, a dedicated Serial Data Line (SDA) and
an Serial Clock Line (SCL) is used. Both SDA and SCL lines are bi-directional.
In multi-master I2C-bus mode, multiple S5PV210 RISC microprocessors receive or transmit serial data to or from
slave devices. The master S5PV210 initiates and terminates a data transfer over the I2C bus. The I2C bus in the
S5PV210 uses a standard bus arbitration procedure.
To control multi-master I2C-bus operations, values must be written to the following registers:
• Multi-master I2C-bus control register- I2CCON
• Multi-master I2C-bus control/status register- I2CSTAT
• Multi-master I2C-bus Tx/Rx data shift register- I2CDS
• Multi-master I2C-bus address register- I2CADD
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