# 15 、FPGA之纯PL流水灯实验

module PL_Led(
clk,
rst_n,
led

);

input clk;
input rst_n;
output [3:0] led;

reg [0:27] cnt;
reg [3:0] led_reg;
always@(posedge clk or negedge rst_n)
if (!rst_n)
begin
cnt<=28'h0000;
end
else if (cnt== 28'h17D_7840) //50MHZ*0.5s
begin
cnt<=28'h0000;
end
else
begin
cnt<=cnt+1'b1;
end

always@(posedge clk or negedge rst_n)
if(!rst_n)
begin
led_reg<=4'b0001;
end
else if (cnt==28'h17D_7840)
begin
led_reg<={led_reg[0],led_reg[3:1]};  //  1 000 0100 0010 0001
end

assign led = led_reg;

endmodule

else if (cnt== 28'h17D_7840) //50MHZ*0.5s

FPGA的开发板的时钟是50MHZ, 计算是1/50MHZ=0.02us秒

0.5s/0.02us=0.5s/(1/50MHZ)=0.5s*50MHZ=0.5*50*1000*1000HZ=25000000=0x17D7840次

set_property PACKAGE_PIN M15 [get_ports {led[3]}]
set_property PACKAGE_PIN G14 [get_ports {led[2]}]
set_property PACKAGE_PIN M17 [get_ports {led[1]}]
set_property PACKAGE_PIN G15 [get_ports {led[0]}]
set_property PACKAGE_PIN K17 [get_ports clk]
set_property PACKAGE_PIN E17 [get_ports rst_n]
set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst_n]

create_clock -period 20.000 -name clk -waveform {0.000 10.000} [get_ports clk]

01-06 1038

01-05 1495

11-27 4612

04-29 372

07-05 51

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07-19 143

11-08 1018