S3C6410 System Clock Controller

    The System Clock Control logic in S3C6410X generates the required system clock signals, ARMCLK for CPU, HCLK for AXI/AHB-bus peripherals, and PCLK for the APB bus peripherals. 

    There are three PLLs in S3C6410X. 

•     One is for ARMCLK only. 
•     Second is for HCLK and PCLK. 
•     The third thing is for peripheral, especially for audio related clocks. 

    The clock control logic generates slow-rate clock-signals for ARMCLK, HCLK and PCLK by bypassing externally supplied clock sources. The clock signal to each peripheral block can be enabled or disabled by software control to reduce the power consumption.

    S3C6410的时钟控制逻辑 即可以外接晶振，然后通过内部电路产生时钟源；也可以直接使用外部提供的时钟源，他们通过引脚的设置来选择。时钟控制逻辑 给整个芯片提供3种时钟：

• ARMCLK用于CPU核；
• HCLK用于AHB总线设备，比如存储控制器，中断控制器，LCD控制器，DMA控制器；
• PCLK用于APB总线上的设备；

    AHB(Advanced High performance Bus)总线主要用于高性能模块(如CPU，DMA和DSP等)之间的连接；

    APB(Advanced Peripheral Bus)总线主要用于底宽带的周边外设之间的连接，例如UART,I2C等。

    S3C6410X has three PLLs which are ：

• APLL for ARM operating clock, 
• MPLL for main operating clock, 
• and EPLL for special purpose. 

    The operating clocks are divided into three groups. 

• The first thing is ARM clock, which is generated from APLL. 
• MPLL generates the main system clocks, which are used for operating AXI, AHB, and APB bus operation. 
• The last group is generated from EPLL. Mainly, the generated clocks are used for peripheral IPs, i.e., UART, IIS, IIC, and etc.

#include "common.h"
#include "regs.h"

/*配置ARMCLK = 533MHZ
      PCLK = 66MHZ
      HCLK = 133MHZ
*/
/*参考S3C6410 P125的图*/
void clock_init(void)
{
	/*把波形锁在PLL中倍频，等频率稳定后输出*/
	APLL_LOCK = 0xffff;//参考S3C6410 P141
	/*配置APLL的倍频系数*/
	APLL_CON = (1 << 31) | (266 << 16) | (3 << 8) | (1 << 0);//参考S3C6410 P141

	OTHERS |= 1 << 6;//参考S3C6410 P169
	MISC_CON &= ~(1 << 19);//参考S3C6410 P168
	CLK_DIV0 = (0 << 0) | (1 << 9) | (1 << 8) | (3 << 12);参考S3C6410 P147
	HCLK_GATE = ~0; //参考S3C6410 P150
	PCLK_GATE = ~0;//参考S3C6410 P150

	CLK_SRC |= 1;//参考S3C6410 P145
}