HDLBITS

link: https://hdlbits.01xz.net/wiki/Fsm_ps2

Fsm ps2

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output done); //

    //IDLE -> FIRST -> SECODN -> THIRD->IDLE
    parameter IDLE=0, FIRST=1,SECOND=2,THIRD=3;
    reg [1:0] state, next_state;
    // State transition logic (combinational)
    always @(*)begin
        next_state=state;
        case(state)
            IDLE:begin
                if(in[3]) next_state=FIRST;
            end
            FIRST:begin
                next_state=SECOND;
            end
            SECOND:begin
                next_state=THIRD;
            end
            THIRD:begin
                if(in[3]) next_state=FIRST;
                else next_state=IDLE;
            end
        endcase
    end
    // State flip-flops (sequential)
    always @(posedge clk, posedge reset)begin
        if(reset)begin
            state<=IDLE;
        end
        else begin
            state<=next_state;
        end
    end
    // Output logic
    assign done=state==THIRD;
endmodule

fsm_ps2data

module top_module(
    input clk,
    input [7:0] in,
    input reset,    // Synchronous reset
    output [23:0] out_bytes,
    output done); //

    // FSM from fsm_ps2

    // New: Datapath to store incoming bytes.
    reg [23:0]out_bytes_r;
    a