S3C6410异常处理机制——异常向量表

摘抄《ARM1176JZF-S™  Technical Reference Manual》中的“Exceptions occurring in Non-secure world”IRQ异常响应

Interrupt request (IRQ) exception

On an Interrupt Request, and CPSR[7]=0, I bit:
/* Non-secure state is unchanged */
if SCR[1]=1 /* IRQ trapped in Secure Monitor mode */
R14_mon = address of the next instruction to be executed + 4
SPSR_mon = CPSR
CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [6] = 1 /* Disable fast interrupts */
CPSR [7] = 1 /* Disable interrupts */
CPSR [8] = 1 /* Disable imprecise aborts */
CPSR [9] = Secure EE-bit /* store value of secure Ctrl Reg bit[25] */
CPSR[24] = 0 /* Clear J bit */
PC = Monitor_Base_Address + 0x00000018
else
R14_irq = address of the next instruction to be executed + 4
SPSR_irq = CPSR
CPSR [4:0] = 0b10010 /* Enter IRQ mode */
CPSR [5] = 0 /* Execute in ARM state */
CPSR [7] = 1 /* Disable interrupts */
If SCR[5]=1 (bit AW)
CPSR [8] = 1 /* Disable imprecise aborts */

Else

CPSR [8] = UNCHANGED
CPSR [9] = Non-secure EE-bit /* store value of NS Control Reg[25] */
CPSR[24] = 0 /* Clear J bit */
if VE == 0 /* Core with VIC port only */
if high vectors configured then
PC = 0xFFFF0018
else
PC = Non_Secure_Base_Address + 0x00000018
else

PC = IRQADDR

其中if high vectors configured then（高地址3G~4G内核空间）

我们裸板开发，则是Non_Secure_Base_Address + 0x00000018

异常向量表：

reset 0x00

Undefined instruction 0x04

Software Interrupt exception 0x08

External Prefetch Abort 0x0c

Internal Prefetch Abort 0x10

Internal Data Abort 0x14

Interrupt request (IRQ) exception      0x18

Fast Interrupt Request (FIQ) exception 0x1c