UART(接收部分)

最新推荐文章于 2024-08-06 18:11:12 发布

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最新推荐文章于 2024-08-06 18:11:12 发布

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分类专栏： FPGA Verilog UART

本文链接：https://blog.csdn.net/u013056038/article/details/47148177

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1、整体框图

文件：UART.v
module UART
(
CLK,nRST,
Rx_Pin_IN,
Rx_En_Sig,
Rx_Done_Sig,
Rx_Data
);
input CLK;
input nRST;
input Rx_Pin_IN;
input Rx_En_Sig;
output Rx_Done_Sig;
output [7:0]Rx_Data;

wire H2L_Sig;
Detect_Module U1
(
.CLK(CLK),.nRST(nRST),
.Pin_IN(Rx_Pin_IN),
.H2L_Sig(H2L_Sig)
);

wire Count_Sig;
wire BPS_CLK;

Rx_Bps_Module U2
(
.CLK(CLK),.nRST(nRST),
.Count_Sig(Count_Sig),
.BPS_CLK(BPS_CLK)
);

Rx_Control_Module U3
(
.CLK(CLK),.nRST(nRST),
.H2L_Sig(H2L_Sig),
.BPS_CLK(BPS_CLK),
.Count_Sig(Count_Sig),
.Rx_Data(Rx_Data),
.Rx_Done_Sig(Rx_Done_Sig),
.Rx_En_Sig(Rx_En_Sig),
.Rx_Pin_IN(Rx_Pin_IN)
);

endmodule

2、子模块
（1）Rx_Bps_Module

文件：Rx_Bps_Module.v
module Rx_Bps_Module
(
CLK,nRST,
Count_Sig,
BPS_CLK
);
input CLK;
input nRST;
input Count_Sig;
output BPS_CLK;

        reg [12:0]Count_BPS;

        always @(posedge CLK or negedge nRST)
             if(!nRST)
                Count_BPS<=13'd0;
             else if(Count_BPS==13'd5207)
                Count_BPS<=13'd0;
             else if(Count_Sig)
                Count_BPS<=Count_BPS+1'd1;
             else 
              Count_BPS<=13'd0;

            assign BPS_CLK=(Count_BPS==2604)?1'b1:1'b0;

            endmodule

（2）Detect_Module

文件：Detect_Module.v
module Detect_Module(CLK,nRST,Pin_IN,H2L_Sig);
input CLK;
input nRST;
input Pin_IN;
output H2L_Sig;

reg H2L_F1;
reg H2L_F2;
always @(posedge CLK or negedge nRST)
if(!nRST)
begin
H2L_F1<=1'b1;
H2L_F2<=1'b1;
end
else
begin
H2L_F1<=Pin_IN;
H2L_F2<=H2L_F1;
end

assign H2L_Sig=H2L_F2&!H2L_F1;

endmodule
（3）Rx_Control_Module

文件：Rx_Control_Module.v
module Rx_Control_Module
(
CLK,nRST,
H2L_Sig,Rx_Pin_IN,
BPS_CLK,Rx_En_Sig,
Count_Sig,Rx_Data,
Rx_Done_Sig
);
input CLK;
input nRST;
input H2L_Sig;
input Rx_Pin_IN;
input Rx_En_Sig;
input BPS_CLK;
output Count_Sig;
output [7:0]Rx_Data;
output Rx_Done_Sig;

reg [3:0]i;
reg [7:0]rData;
reg isCount;
reg isDone;

always @(posedge CLK or negedge nRST)
if(!nRST)
begin
i<=4'd0;
isCount<=1'b0;
rData<=8'd0;
isDone<=1'b0;
end
else if(Rx_En_Sig)
case(i)
4'd0:if(H2L_Sig)begin i<=i+1'b1; isCount<=1'b1;end//检测到起始位，拉高isCount使Rx_BPS_Module产生波特率

     4'd1:if(BPS_CLK)i<=i+1'b1;//忽略起始位

     4'd2,4'd3,4'd4,4'd5,
     4'd6,4'd7,4'd8,4'd9:if(BPS_CLK)
                         begin i<=i+1'b1; rData[i-2]<=Rx_Pin_IN;end//8位数据位

     4'd10:if(BPS_CLK) i<=i+1'b1; //忽略校验位

     4'd11:if(BPS_CLK) i<=i+1'b1; //忽略结束位

     4'd12:begin i<=i+1'b1;isDone<=1'b1;isCount<=1'b0;end    //接受完成，拉高isDone;拉低isCount使Rx_BPS_Module停止产生波特率

    4'd13:begin i<=4'd0;isDone<=1'b0;end    //拉低isDone,等待下一帧数据

   endcase

assign Rx_Data=rData;
assign Rx_Done_Sig=isDone;
assign Count_Sig=isCount;

endmodule