PCIe学习笔记（24）--- PL-Logical (Gen 1 and Gen 2) --- (1)

对应Chapter 11: Physical layer- logical (Gen 1 and Gen2)

TX: 

D-DATA/K-CONTROL: 

Gen1/2是区分D/K symbol的，所以有D/K# bit

Gen3没有K symbol, 128 bit (16 bytes) data block中， 有2 bit的SYNC HEADER, 其中包含的信息，让RECEIVER知道，是TLP/DLLP还是OS

Striped:

将PACKET中的BYTES分散到LINK中的每一条LANE上去

Scramble:

COM K Symbol: reset scrambler

Gen 3, 24-bit based scrambler （Gen 1/2, 16-bit ）

Character to Symbol:

Gen 1/2: 8b/10b encoder

Gen 3: 128/130b encoding scheme

RX:

CDR: 

clock data recovery, recovered clock based on transitions in the incoming bit stream

Gen1/2: symbol lock, 

Gen3: block lock

Elastic buffer:

SKP SYMBOLS

Un-striped: