题目如图下;
代码如下:
module cnt(clk,rst_n,en,dout);
input wire clk;
input wire rst_n;
input wire en;
output reg dout;
reg [4-1:0]cnt;
wire add_cnt;
wire end_cnt;
assign add_cnt=(dout==1);
assign end_cnt=add_cnt&&(cnt==9);
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
begin
cnt<=0;
end
else if(add_cnt)
begin
if(end_cnt)
cnt<=0;
else
cnt<=cnt+1;
end
end
always@(posedge clk or negedge rst_n)
begin
if(!rst_n)
dout<=0;
else
if(en==1)
dout<=1;
if(end_cnt)
dout<=0;
end
endmodule
testbench:
`timescale 1ns/1ns
module tb_cnt;
reg clk;
reg rst_n;
reg en;
wire dout;
initial
begin
clk=0;
rst_n=0;
en=0;
#1000 rst_n=1;
#20 en=1;
#20 en=0;
end
always #10 clk=~clk;
cnt cnt(
.clk(clk),
.rst_n(rst_n),
.en(en),
.dout(dout)
);
endmodule
仿真结果如下: